In this letter, a simple design of a discrete-time chaos circuit realizing a tent map is proposed. The proposed circuit can be constructed with 13 MOSFET's and 2 capacitors. Concerning the proposed circuit synthesized using switched-current (SI) techniques, the validity of the circuit design is analyzed by SPICE simulations. Furthermore, the proposed circuit is built with commercially-available IC's. The proposed circuit is integrable by a standard CMOS technology.

A low-ripple diode charge-pump type AC-DC converter based on the Cockcroft-Walton diode multiplier is proposed for coil-coupled passive IC tags in this paper. This circuit is developed as a power supply for passive RFID tags with smart functions such as heart rate detection and/or body temperature measurement. The proposed circuit converts wirelessly induced power to a low-ripple DC voltage suitable for a 13.56 MHz RFID tag. The proposed circuit topology and the principle of operation are explained and treated theoretically by using quasi-equivalent small-signal models. The proposed circuit was implemented on a PCB. And it was confirmed that the proposed circuit provides 3.3 V DC with a ripple of less than 20 mV when a 4 Vp-p sinusoidal input is applied. Under this condition, the maximum output power is about 310 µW. The measured results were in good agreement with theoretical and HSPICE simulation results.

A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 µW at fOSC=13.56 MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC=13.56 MHz thanks to the use of composite high-impedance current sources.

We propose feedback-limited NFSRs (nonlinear feedback shift registers) which can generate periodic sequences of period 2k-1, where k is the length of the register. We investigate some characteristics of such periodic sequences. It is also shown that the scale of such NFSRs can be reduced by the feedback limitation. Some simulation and experimental results are shown including comparison with LFSRs (linear feedback shift registers) for conventional M-sequences and Gold sequences.

A low-sensitivity bandpass switched-capacitor filter (SCF) using two-path and voltage inversion techniques is proposed. The worstcase sensitivity of this SCF becomes zero at the center frequency. The proposed SCF is fully parasitic insensitive and requires a four-phase clock.

A capacitor-error-free SC voltage inverter with zero sensitivity to element-value variations is proposed. By virtue of the capacitor-error-free property, this SC voltage inverter is free from the capacitor mismatch. The performance of this SC voltage inverter has been confirmed from both the simulation and experiment.

For a realization of a DC-DC converter using no magnetic devices, a new switched capacitor (SC) transformer is introduced, which gives voltage ratios by Fibonacci series corresponding to the stages. This transformer is connected in cascade by each basic block which is assembled by a capacitor and three MOSFET switches. This operates on a simple two-phase clock and has a large step-up or step-down voltage ratio in spite of its simple configuration. The characteristics of this transformer with n stages of basic block are derived and calculated by means of a 4 4 cascade matrix. The optimal arrangement of each stage's capacitances is shown to reduce the SC resistance by about 20%. The simulation results are compared with the characteristics of a prototype transformer with four stages (8 times step-up ratio). Its power efficiency achieves 88% in case of 97 V output voltage, 0.2 A output current, and 100 kHz switching frequency. Lastly, the proposed SC transformer is compared and discussed with other typical SC transformers.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

New cyclic switched-capacitor (SC) D/A and A/D converters are proposed. In the former, a capacitor-mismatch-compensation technique using additional small capacitors is introduced. With this, a capacitor ratio accuracy as high as twelve bits is possible. And, in the latter, the A/D conversion with ten-bit accuracy is realizable by the simple ratio-independent circuit consuming only a few number of clock cycles for each bit conversion.

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

New AC-DC converters using switched-capacitor (SC) transformers are presented. The features of these circuits are as follows. (1) It does not contain any magnetic material. (2) The inrush current of the proposed converter is very small as compared with that of a condenser-input-type rectifier circuit. (3) It is realizable in a hybrid IC form. (4) It excels in size and weight when compared with reactor-type switching regulators of the same output power. As an example, an AC-DC converter using step-up SC transformers was built and tested to confirm the characteristics. The measured characteristics showed good agreement with the calculated ones.

This paper deals with the method for generation of maximal-period sequences which are designed by properly quantizing the variable state of a class of one-dimensional piecewise-linear onto maps. We confirmed that the proposed method enables us to generate many maximal-period sequences from such maps including De-Bruijn cases.

This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

A method for circular pattern recognition in a binary image and its implementation onto an FPGA are described. The proposed method is based on the template matching method using a modified matching degree. This method is implementable onto an FPGA and can realize a real-time system. The usefulness of the proposed method was confirmed by numerical simulations. The real-time performance was confirmed by experiments on the FPGA designed by using Verilog-HDL CAD tool.

A maximum and a minimum circuits with multiple inputs are proposed. The operating speeds of these circuits are independent of the number of the inputs. Since the proposed circuits consist of only NMOS transistors, they can be implemented in semi-custom IC forms. A potential application of these circuits is a real-time fuzzy controller.

This paper proposes a novel quad-band branched monopole antenna with a filter. The proposed antenna has a simple configuration in which branch-elements are added to a basic configuration consisting of a mast and dielectric wires. The antenna is characterized by performances such as wideband impedance matching, gain stabilization, and gain enhancement. Wideband impedance characteristics satisfying the voltage standing ratio of less than 2 are obtained by exciting a parallel resonance at the lowest band and multi-resonance at high bands. The filter suppressing higher order modes is used for gain stabilization, so that averaged gains above 5dBi are obtained at the quad-band. The antenna has a high gain of 11.1dBi because the branch-elements work as an end-fire array antenna at the highest band. Furthermore, it is clarified that an operating frequency is switched by using a variable bandpass filter at the lowest band. Last, a scale model of the antenna is fabricated and measured, then the effectiveness of the proposed antenna is demonstrated.

New OTA-based analog circuits for realizing fuzzy membership functions and maximum (MAX) and minimum (MIN) operations are proposed. The synthesis of these circuits based on a bounded-difference operation and their SPICE simulations are described.

This paper presents design of spreading codes for asynchronous DS-CDMA systems. We generate maximal-period sequences with negative auto-correlations based on one-dimensional maps with finite bits whose shapes are similar to piecewise linear chaotic maps. We propose an efficient search algorithm to find such maximal-period sequences. This algorithm makes it possible to find many kinds of maximal-period sequences with sufficiently long period for practical CDMA applications. We also report that maximal-period sequences can outperform conventional Gold sequences in terms of bit error rate (BER) in asynchronous DS-CDMA systems.