Toshitada SAITO Mario TOKORO Hideharu AMANO
Ethernet is a scheme of local computer networking, which has been widely utilized. Acknowledging Ethernet insures immediate acknowledgement by providing an acknowledgement mechanism in the MAC (Media Access Control) layer protocol. Although Acknowledging Ethernet gives both higher reliability and higher performance, this scheme is not compatible with DIX or IEEE 802 Ethernet. In this paper, a modified scheme which is compatible with the original Ethernet, called the Compatible Acknowledging Ethernet (CAE), is proposed. The CAE scheme allows sharing of the same cable with Ethernet. CAE can be implemented by adding a small amount of logic to the Network Interface Unit of the original Ethernet.
Mitsuhiro TATEDA Shin-ichi FURUKAWA Hiromichi MIYOKAWA
The feasibility of a 1600 mechanical optical switch is demonstrated. The maximum insertion loss is 0.2 dB and the loss variation throughout 500 switching cycles is less than 0.1 dB for both multimode and single-mode fibers at wavelengths of 0.85, 1.3, and 1.53 µm. The maximum switching time is 3.4 seconds.
Tao LIN Masayuki KAWAMATA Tatsuo HIGUCHI
The average coefficient sensitivity is defined for 2-D systems described by Roesser's local state space model. The sensitivity can be computed by using the 2-D observability Gramian and the 2-D controllability Gramian, which are also called the 2-D noise matrix and the 2-D covariance matrix if the 2-D systems are considered to be 2-D digital filters. Minimization of sensitivity via 2-D equivalent transforms is studied in cases of having no constraint and having a scaling constraint on the state vector. In the first case, the minimum sensitivity realizations are equivalent to the 2-D balanced realizations modulo a block orthogonal transform. In the second case, the 2-D systems are considered to be 2-D digital filters and the minimization of sensitivity is equivalent to the minimization of roundoff noise under l2-norm scaling constraint. An example is given to show method of analysing and minimizing the sensitivity of 2-D systems.
Moon Soo KIM Nobuhiro TOMABECHI
This paper discusses an efficient implementation of fault-tolerant digital filters based on the residue number system. In this implementation, a compact residue arithmetic module named the pulse-train residue arithmetic circuit" is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detections is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. Two design methods of fault-tolerant digital filters are newly proposed. In one method the error correcting circuit is imposed in series to the non-redundant system, and in the other the one is imposed in parallel. The prior has an advantage of compact hardware, and the latter has an advantage of high-speed operation. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter with 3 digits is practically implemented, and its fault-tolerant ability is proved by noise injection testing. It is found that the hardware of our digital filter is 70% of the one based on the conventional tripple modular redundancy (TMR), and the mission time improving factor of our digital filter is 150% of the one of the TMR system.
The performances of parametric receivers such as the linear, the maximum likelihood and the hard limiter have been analyzed before for the detection of frequency-hopped multilevel frequency-shift keyed signals (FH-MFSK) in mobile radiotelephony. Also, nonparametric receivers such as the maximum rank sum receiver (MRSR) and the reduced rank sum receiver (RRR) were previously considered. Here, a receiver called the mean level receiver (MLR) is analyzed. It is neither parametric nor nonparametric. It depends on the noise (or interference) distribution except for a scale parameter which may correspond to the noise power. The proposed receiver is distinguished by its easier implementation, constant false alarm rate and relatively good performance.
Yuhki IMAI Kuniki OHWADA Yoshihiro IMAMURA
A new self-aligned recessed-gate GaAs MESFET is developed using RIBE for recess etching. Recess-etching depth can be precisely controlled by RIBE with BCl3 etching gas. Barrier height and ideality factor of the Schottky contact formed on 200-V bias-voltage RIBE etched surface are 0.8 V and 1.2, respectively after 400 annealing. A very short gate-length is realized simply using the sidewall formation and the conventional photolithography. Furthermore, a self-alignment of ohmic electrodes and N+-layers to a gate electrode is realized to minimize the source resistance. The 0.3-µm gate-length MESFET fabricated on a wafer with the carrier concentration of 1.21018 cm-3 grown by MBE shows the transconductance as high as 415 mS/mm.
Shoji SHINODA Shuji TSUKIYAMA Isao SHIRAKAWA
Let G be a directed graph containing n nodes and m edges, with each edge of nonnegative length. Given two specified nodes s and t, the length of a k-tuple of edge-disjoint paths from s to t in G is the sum of the lengths of all the edges on these k paths. A polynomial time algorithm for finding a shortest k-tuple of edge-disjoint paths from s to t in G has been devised. Based on this algorithm, this paper considers the problem of finding a second shortest k-tuple of edge-disjoint paths from s to t in G, for which an O (min[n3, nm log n])-time is described.
Issam A. HAMID Norio SHIRATORI Shoichi NOGUCHI
The system performance is greatly affected by the interprocessor communication, which should be enough to support the various types of permutations functions for the mapping purposes. But if there are many types of manipulations, it becomes necessary to have a rearrengeable IN like the Benes Interconnection Network (IN) so that we can increase the number of stages to 2n-1, where N=2n, and N is the number of input terminals which is base 2. But the control algorithm for this kind of IN is very complex. In this paper we have studied the mapping capabilities of Benes IN to be used into super system and we give a control algorithms for setting this network for groups of manipulation functions proved to be efficiently useful for parallel computation. We have also, shown how to enhance these control algorithm to be used by the system programmers with examples. Also, we have given cases studies for kinds of applications to be applicable in such system, so that to realize the effectiveness of such mechanism.
With respect to the power reed switch connected with a long cable, there could be found a peculiar phenomenon that the longer the cable was, the longer the switching life was. Furthermore, the switching life was largely improved by using the contacts in combination with foreign materials.
Employing the quick action mechanism and the contacts in combination with foreign materials Mo and AgCdO, a new type of power reed switch featuring high reliability and large switching capacity was successfully developed.
Mohsen GHAMESHLU Noriyoshi YOSHIDA
Layering problem of multilayer printed wiring boards in the single-row routing approach is considered. For use in high density printed wiring boards, an extended layering algorithm is proposed for the case of street capacity K2, while all conventional algorithms are for K=2.
Optical signal processors consisting of integrated collinear acousto-optic modulators are proposed. In this device, wavelength-multiplexed optocal signals can be dealed with independently to each other by frequency-multiplexed surface acoustic waves. As applications to optical computing, several architectures performing matrix-vector and matrix-matrix multplications are discussed. Twos-complement arithmetic is also employed to improve accuracy and to handle bipolar numbers. The processing rate of matrix-vector multiplication is estimated to be 51010 and 3108 multiplication/sec. for analog and binary representations, respectively.
A sufficient condition is given for the waveform relaxation algorithm based on an asynchronous iteration to converge uniformly.
This paper presents a hole coupling theory for the directional coupler to monitor the output of Gyrotron. The theory gives an expression for a hole coupling coefficient including the wall thickness effect.
Tuptim ANGKAEW Masanori MATSUHARA Nobuaki KUMAGAI
An improved finite-element formulation using quadratic shape functions is presented. The improvement in accuracy of the method is investigated in comparative to the case of using linear shape functions. As an example of using the quadratic shape functions, an accurate analysis of a microstrip waveguide has been carried out. Good agreement between the finite-element solutions and the other numerical solutions is confirmed. This agreement shows the validity and usefulness of the method.
Rate-distortion theory for the points that are distributed with the uniform density (Poisson point processes) is studied. The rate-distortion function per point for n neighboring points Rn(D) is introduced and the function R (D) is defined as a limitting function of Rn(D) for infinitely large n. A Shannon lower bound for the rate-distortion function is obtained and it is shown that the rate-distortion function for an interval length between neighboring points is the better lower bound. The behavior of Dmax(n), the value of D where Rn(D) first reaches zero, is studied. A coding scheme that constitutes an upper bound to R(D) is evaluated and it is shown that the rate-distortion function for the corresponding Wiener process is the better upper bound for large distortion. Some discussions are made on the coding theorem for our problem.
This paper discusses the approximate solution to the weighted graph matching problem (WGMP) both for undirected and directed graphs. WGMP is the problem of finding the optimum matching between two weighted graphs, which are graphs with weights at each arc. The proposed method employs an analytic approach using the eigen-decomposition of the adjacency matrix (in the case of undirected matching problem) or the singular value decomposition of the incidence matrix (in the case of directed graph matching problem) of a given graph. A technique for reducing the execution time to search for the solution is given. Simulation experiments are also given to evaluate the performance of the proposed method.
One odd property of the purely random sequences is introduced: In the sample autocovariance of the purely random sequence the squared magnitude at the origin tends to the sum of the squared magnitudes except at the origin irrespective of the type of its probability distribution function. Further expressing the above property in the frequency domain we give the different approach to prove the known fact that the power spectrum of the purely random sequence is always different from its periodogram even if the number of sample points tend to infinity. Finally, as an application we show that the noise periodogram can be estimated from the image degraded by the additive noise.
Yoshihide IGARASHI Kazuhiro SADO Koji SAGA
We discuss time lower bounds for iterative merge sorts and iterative psueudo-merge sorts on an nn meshconnected processor array. They are 4.5n-3log2n-2 steps and 3.5n-log2n-3 steps for sorting n2 items. We also discuss time lower bounds for these sorting algorithms on higher dimensional models. For the case of the three-dimensional mesh-connected model, 7.25n-4log2n-8 steps and 5.25n-log2n-6 steps are lower bounds for sorting n3 items by iterative merge sorts and iterative pseudo-merge sorts, respectively.
An enhanced temperature dependence of drain saturation current as well as threshold voltage is observed for ion-implanted GaAs MESFET's when backgate or sidegate bias voltage is applied. By performing conductance DLTS measurement based on backgating effect of FETs, three kind of traps, namely Cr, HL4 and HL8, are identified for the substrate prepared by Horizontal Bridgman method. Also three kind of traps, namely EL2, HL4 and HL8, are identified for the non-doped Liquid Encapsulated Czochlalski (LEC) substrate. Simulation of the stationary characteristics of FETs is made at various temperature using a device model which includes both the depletion region at the n-i (channel-substrate) junction and influence of the deep traps. A model in which some other deep traps than EL2 are localized in the vicinity of n-i junction explains well the enhanced temperature dependence of saturation current. In addition to EL2, important contribution of hole traps to the FET characteristics is suggested for the devices prepared on the undoped LEC substrate by ion-implantation.