We propose a novel single polarization photonic band gap fiber (SP-PBGF) with an anisotropic air hole lattice in the core. An SP-PBGF with an elliptical air hole lattice in the core recently proposed can easily realize SP guidance utilizing the large difference of cutoff frequency for the x- and y-polarized modes. In this paper, in order to achieve SP guidance based on the same principle of this PBGF, we utilize an anisotropic lattice of circular air holes instead of elliptical air holes to ease the fabrication difficulty. After investigating the influence of the structural parameters on SP guidance, it is numerically demonstrated that the designed SP-PBGF has 381 nm SP operating band.

In this paper, a multiple-object tracking approach in large-scale scene is proposed based on visual sensor network. Firstly, the object detection is carried out by extracting the HOG features. Then, object tracking is performed based on an improved particle filter method. On the one hand, a kind of temporal and spatial dynamic model is designed to improve the tracking precision. On the other hand, the cumulative error generated from evaluating particles is eliminated through an appearance model. In addition, losses of the tracking will be incurred for several reasons, such as occlusion, scene switching and leaving. When the object is in the scene under monitoring by visual sensor network again, object tracking will continue through object re-identification. Finally, continuous multiple-object tracking in large-scale scene is implemented. A database is established by collecting data through the visual sensor network. Then the performances of object tracking and object re-identification are tested. The effectiveness of the proposed multiple-object tracking approach is verified.

In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a multi-scenario high-level synthesis algorithm for variation-tolerant floorplan-driven design targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. At that time, we can explicitly take into account interconnection delays by using distributed-register architectures. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.

SDN (Software-Defined Networking) enables software applications to program individual network devices dynamically and therefore control the behavior of the network as a whole. Incomplete programming and/or inconsistency with the network policy of SDN software applications may lead to verification issues. The objective of this paper is to describe the formal modeling that uses the process algebra called pACSR and then suggest a method to verify the firewall application running on top of the SDN controller. The firewall rules are translated into a pACSR process which acts as the specification, and packet's behaviors in SDN are also translated to a pACSR process which is a role as the implementation. Then we prove the correctness by checking whether the parallel composition of two pACSR processes is deadlock-free. Moreover, in the case of network topology changes, our verification can be directly applied to check whether any mismatches or inconsistencies will occur.

In most existing centralized lighting control systems, the lighting control problem (LCP) is reformulated as a constrained minimization problem and solved by linear programming (LP). However, in real-world applications, LCP is actually discrete and non-linear, which means that more accurate algorithm may be applied to achieve improvements in energy saving. In this paper, particle swarm optimization (PSO) is successfully applied for office lighting control and a linear programming guided particle swarm optimization (LPPSO) algorithm is developed to achieve considerable energy saving while satisfying users' lighting preference. Simulations in DIALux office models (one with small number of lamps and one with large number of lamps) are made and analyzed using the proposed control algorithms. Comparison with other widely used methods including LP shows that LPPSO can always achieve higher energy saving than other lighting control methods.

An efficient three-dimensional (3-D) fundamental locally one-dimensional finite-difference time-domain (FLOD-FDTD) method incorporated with memristor is presented. The FLOD-FDTD method achieves higher efficiency and simplicity with matrix-operator-free right-hand sides (RHS). The updating equations of memristor-incorporated FLOD-FDTD method are derived in detail. Numerical results are provided to show the trade-off between efficiency and accuracy.

The goal of software testing should go beyond simply finding defects. Ultimately, testing should be focused on increasing customer satisfaction. Defects that are detected in areas of the software that the customers are especially interested in can cause more customer dissatisfaction. If these defects accumulate, they can cause the software to be shunned in the marketplace. Therefore, it is important to focus on reducing defects in areas that customers consider valuable. This article proposes a value-driven V-model (V2 model) that deals with customer values and reflects them in the test design for increasing customer satisfaction and raising test efficiency.

SSDs consist of non-mechanical components (host interface, control core, DRAM, flash memory, etc.) whose integrated behavior is not well-known. This makes an SSD seem like a black-box to users. We analyzed power consumption of four SSDs with standard I/O operations. We find the following: (a) the power consumption of SSDs is not significantly lower than that of HDDs, (b) all SSDs we tested had similar power consumption patterns which, we assume, is a result of their internal parallelism. SSDs have a parallel architecture that connects flash memories by channel or by way. This parallel architecture improves performance of SSDs if the information is known to the file system. This paper proposes three SSD characterization algorithms to infer the characteristics of SSD, such as internal parallelism, I/O unit, and page allocation scheme, by measuring its power consumption with various sized workloads. These algorithms are applied to four real SSDs to find: (i) the internal parallelism to decide whether to perform I/Os in a concurrent or an interleaved manner, (ii) the I/O unit size that determines the maximum size that can be assigned to a flash memory, and (iii) a page allocation method to map the logical address of write operations, which are requested from the host to the physical address of flash memory. We developed a data sampling method to provide consistency in collecting power consumption patterns of each SSD. When we applied three algorithms to four real SSDs, we found flash memory configurations, I/O unit sizes, and page allocation schemes. We show that the performance of SSD can be improved by aligning the record size of file system with I/O unit of SSD, which we found by using our algorithm. We found that Q Pro has I/O unit of 32 KB, and by aligning the file system record size to 32 KB, the performance increased by 201% and energy consumption decreased by 85%, which compared to the record size of 4 KB.

This paper proposes a static application mapping technique, based on integer linear programming, for non-hierarchical manycore embedded systems. Unlike previous work which was designed for hierarchical manycore SoCs, this work allows more flexible application mapping to achieve higher performance. The experimental results show the effectiveness of this work.

The reputation-based majority-voting approach is a promising solution for detecting malicious workers in a cloud system. However, this approach has a drawback in that it can detect malicious workers only when the number of colluders make up no more than half of all workers. In this paper, we simulate the behavior of a reputation-based method and mathematically analyze its accuracy. Through the analysis, we observe that, regardless of the number of colluders and their collusion probability, if the reputation value of a group is significantly different from those of other groups, it is a completely honest group. Based on the analysis result, we propose a new method for distinguishing honest workers from colluders even when the colluders make up the majority group. The proposed method constructs groups based on their reputations. A group with the significantly highest or lowest reputation value is considered a completely honest group. Otherwise, honest workers are mixed together with colluders in a group. The proposed method accurately identifies honest workers even in a mixed group by comparing each voting result one by one. The results of a security analysis and an experiment show that our method can identify honest workers much more accurately than a traditional reputation-based approach with little additional computational overhead.

Because wavelet transforms have the characteristic of decomposing signals that are similar to the human acoustic system, speech enhancement algorithms that are based on wavelet shrinkage are widely used. In this paper, we propose a new speech enhancement algorithm of hearing aids based on wavelet shrinkage. The algorithm has multi-band threshold value and a new wavelet shrinkage function for recursive noise reduction. We performed experiments using various types of authorized speech and noise signals, and our results show that the proposed algorithm achieves significantly better performances compared with other recently proposed speech enhancement algorithms using wavelet shrinkage.

In the development of inter-vehicle communication systems for a prevention of car crashes, it is important to know path loss characteristics at blind intersections in urban area. Thus field experiments and numerical simulations have been performed. By the way, transparent waves from building walls are not considered in many cases. The reason why is that it is the worst case in terms of the path loss at blind intersection surrounded by buildings in urban area. However, it would be important to know the effect of transparent wave on the path loss in actual environments. On the other hand, path loss models have been proposed to estimate easily the path loss in urban environment. In these models, the effect of transparent wave is not clear. In this paper, the effect of transparent wave from building walls on path loss characteristics at blind intersection in urban area is investigated by using the FDTD method. Additionally, the relationship between transparent wave and path loss models is also investigated.

We present a design method for miniaturizing double stub resonators that are potentially very useful for wide range of applications but have limited usage for MMICs due to their large footprint. The analytical design model, which we introduce in this paper, allows for determining the capacitances needed to achieve the targeted shrinking ratio while maintaining the original loaded-Q before miniaturization. To verify the model, 18-GHz stub resonators that are around 40% of the original sizes were designed and fabricated in GaAs MMIC technology. The effectiveness of the proposed technique is also demonstrated by a 9-GHz low phase-noise oscillator using the miniaturized resonator.

Pre-Cantor bar, the one-dimensional fractal media, consists of two kinds of materials. Using the transmission-line theory we will explain the double-exponential behavior of the minimum of the transmittance as a function of the stage number n, and obtain formulae of two kinds of scaling behaviors of the transmittance. From numerical calculations for n=1 to 5 we will find that the maximum of field amplitudes of resonance which increases double-exponentially with n is well estimated by the theoretical upper bound. We will show that after sorting field amplitudes for resonance frequencies of the 5th stage their distribution is a staircase function of the index.

SM3 is a hash function standard defined by China. Unlike SHA-1 and SHA-2, it is hard for SM3 to speed up the throughput because it has more complicated compression function than other hash algorithm. In this paper, we propose a 4-round-in-1 structure to reduce the number of rounds, and a logical simplifying to move 3 adders and 3 XOR gates from critical path to the non-critical path. Based in SMIC 65nm CMOS technology, the throughput of SM3 can achieve 6.54Gbps which is higher than that of the reported designs.

This paper considers on-demand WiFi wake-up where a wake-up receiver is installed into each WiFi device. The wake-up receiver detects a wake-up call by finding the predefined length of WiFi frames, which corresponds to a wake-up ID, through envelope detection with limited signal processing. Since each wake-up receiver continuously observes the WiFi channel, an adverse event of False Positive (FP), where a WiFi device is falsely turned on without actual wake-up calls, can occur when the length of non-wake-up, background data frames match with predefined length. In this paper, we suggest using the received signal strength (RSS) of WiFi frames to differentiate the real and false wake-up calls. The proposed scheme exploits the correlation among RSSs of WiFi frames received from a single station located in a fixed position. Using measured RSS data obtained under various settings and different degrees of mobility, we investigate not only the FP reduction rate but also its impact on the probability of detecting real wake-up calls. We also present experimental results obtained with our prototype in which the proposed scheme is implemented.

The single-shot collision attack on RSA proposed by Hanley et al. is studied focusing on the difference between two operands of multiplier. It is shown that how leakage from integer multiplier and long-integer multiplication algorithm can be asymmetric between two operands. The asymmetric leakage is verified with experiments on FPGA and micro-controller platforms. Moreover, we show an experimental result in which success and failure of the attack is determined by the order of operands. Therefore, designing operand order can be a cost-effective countermeasure. Meanwhile we also show a case in which a particular countermeasure becomes ineffective when the asymmetric leakage is considered. In addition to the above main contribution, an extension of the attack by Hanley et al. using the signal-processing technique of Big Mac Attack is presented.

A novel resilient coarse granularity optical routing network architecture that adopts finely granular protection and finely granular add/drop is presented. The routing scheme defines optical pipes such that multiple optical paths can be carried by each pipe and can be dropped or added at any node on the route of a pipe. The routing scheme also makes it possible to enhance frequency utilization within pipes, by denser path packing in the frequency domain, as we recently verified. We develop a static network design algorithm that simultaneously realizes the independence of working and backup paths and pipe location optimization to efficiently carry these paths. The design algorithm first sequentially accommodates optical paths into the network, then tries to eliminate sparsely utilized fibers and iteratively optimizes frequency slot/wavelength assignment in each coarse granular pipe so as to limit the impairment caused by dropping the optical paths adjacent in the frequency domain. Numerical experiments elucidate that the number of fibers in a network can be reduced by up to 20% for 400Gbps channels without any modification in hardware.

Recently, due to the development of design and manufacturing technologies for VLSI systems, an embedded system becomes more and more complex. Consequently, not only the performance of chips, but also the flexibility and dynamic adaptation of the implemented systems are required. To achieve these requirements, a partially reconfigurable device is promising. In this paper, we propose an efficient data structure to manage the reconfigurable units. And then, on the assumption that each task utilizes the rectangle shaped resources, a very simple MER enumeration algorithm based on this data structure is proposed. By utilizing the result of MER enumeration, the free space on the reconfigurable device can be used sufficiently. We analyze the complexity of the proposed algorithm and confirm its efficiency by experiments.

In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, circuit performance is expected to be improved compared to complete-synchronous framework, in which the clock is distributed periodically and simultaneously to each register. To improve the circuit performance more, logic synthesis for general-synchronous framework is required. In this paper, under the assumption that any clock schedule is realized by an ideal clock distribution circuit, when two or more cell libraries are available, a technology mapping method which assigns a cell to each gate in the given logic circuit by using integer linear programming is proposed. In experiments, we show the effectiveness of the proposed technology mapping method.