In this paper, a Many Integrated Core Architecture (MIC) accelerated parallel method of moment (MoM) algorithm is proposed to solve electromagnetic problems in practical applications, where MIC means a kind of coprocessor or accelerator in computer systems which is used to accelerate the computation performed by Central Processing Unit (CPU). Three critical points are introduced in this paper in detail. The first one is the design of the parallel framework, which ensures that the algorithm can run on distributed memory platform with multiple nodes. The hybrid Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) programming model is designed to achieve the purposes. The second one is the out-of-core algorithm, which greatly breaks the restriction of MIC memory. The third one is the pipeline algorithm which overlaps the data movement with MIC computation. The pipeline algorithm successfully hides the communication and thus greatly enhances the performance of hybrid MIC/CPU MoM. Numerical result indicates that the proposed algorithm has good parallel efficiency and scalability, and twice faster performance when compared with the corresponding CPU algorithm.

A 62ps timing resolution pulse generator (PG) is presented. The PG adopts the multi-phase ring oscillator and the pulse combiner circuit (PCC) to achieve the low timing error. The PCC can decide an arbitrary waveform via 16 phase outputs. PCC adopts the coarse-tuning stage (CTS) and the fine-tuning (FTS) to define the operational frequency range and the timing resolution, respectively. Hence, PCC uses edge combiner (EC) to combine the period window of CTS. The latency of PG is only 3 cycle times. The operational frequency range of PG is from 15MHz to 245MHz. The timing resolution and average accuracy of PG are 62.5ps and ±0.5 LSB, respectively. The RMS jitter and peak-to-peak jitter of PG are 6.55ps and 66.67ps, respectively, at 245MHz.

In this paper, a novel multilayer substrate integrated waveguide (SIW) four-way out-of-phase power divider is proposed. It is realized by 3D mode coupling, on multilayer substrates. The structure consists of vertical Y-junction, lateral T-junction of SIW and lateral Y-junction of half-mode SIW. The advantages of the proposed structure are its low cost and ease of fabrication. Also, it can be integrated easily with other planar circuits such as microstrip circuits. An experimental circuit is designed and fabricated using the traditional printed circuit board technology. The simulated and measured results show that the return loss of the input port is above 15 dB over 8 to 11.8 GHz and transmissions are about -7.6±1.6 dB in the passband. It is expected that the proposed the proposed power divider will play an important role in the future integration of compact multilayer SIW circuits and systems.

Let G be a probabilistic graph, in which the vertices fail independently with known probabilities. Let K represent a specified subset of vertices. The K-terminal reliability of G is defined as the probability that all vertices in K are connected. When |K|=2, the K-terminal reliability is called the 2-terminal reliability, which is the probability that the source vertex is connected to the destination vertex. The problems of computing K-terminal reliability and 2-terminal reliability have been proven to be #P-complete in general. This work demonstrates that on multi-tolerance graphs, the 2-terminal reliability problem can be solved in polynomial-time and the results can be extended to the K-terminal reliability problem on bounded multi-tolerance graphs.

The software birthmarking technique has conventionally been studied in fields such as software piracy, code theft, and copyright infringement. The most recent API-based software birthmarking method (Han et al., 2014) extracts API call sequences in entire code sections of a program. Additionally, it is generated as a birthmark using a cryptographic hash function (MD5). It was reported that different application types can be categorized in a program through pre-filtering based on DLL/API numbers/names. However, similarity cannot be measured owing to the cryptographic hash function, occurrence of false negatives, and it is difficult to functionally categorize applications using only DLL/API numbers/names. In this paper, we propose an API-based software birthmarking method using fuzzy hashing. For the native code of a program, our software birthmarking technique extracts API call sequences in the segmented procedures and then generates them using a fuzzy hash function. Unlike the conventional cryptographic hash function, the fuzzy hash is used for the similarity measurement of data. Our method using a fuzzy hash function achieved a high reduction ratio (about 41% on average) more than an original birthmark that is generated with only the API call sequences. In our experiments, when threshold ε is 0.35, the results show that our method is an effective birthmarking system to measure similarities of the software. Moreover, our correlation analysis with top 50 API call frequencies proves that it is difficult to functionally categorize applications using only DLL/API numbers/names. Compared to prior work, our method significantly improves the properties of resilience and credibility.

Designing secure revocable storage systems for a large number of users in a cloud-based environment is important. Cloud storage systems should allow its users to dynamically join and leave the storage service. Further, the rights of the users to access the data should be changed accordingly. Recently, Liang et al. proposed a cloud-based revocable identity-based proxy re-encryption (CR-IB-PRE) scheme that supports user revocation and delegation of decryption rights. Moreover, to reduce the size of the key update token, they employed a public key broadcast encryption system as a building block. In this paper, we show that the CR-IB-PRE scheme with the reduced key update token size is not secure against collusion attacks.

Fast identification is an urgent demand for modern RFID systems. In this paper, we propose a novel algorithm, access probability adjustment based fine-grained Q-algorithm (APAFQ), to enhance the efficiency of RFID identification with low computation overhead. Specifically, instead of estimation accuracy, the target of most proposed anti-collision algorithms, the APAFQ scheme is driven by updating Q value with two different weights, slot by slot. To achieve higher identification efficiency, the reader adopts fine-grained access probability during the identification process. Moreover, based on the responses from tags, APAFQ adjusts the access probability adaptively. Simulations show the superiority of APAFQ over existing Aloha-based algorithms.

In this paper, we have investigated a new structure which combines dielectric cylinders with air-hole cylinders array, and analyzed the guiding problem for periodically dielectric waveguides by arbitrary shape of dielectric constants in the middle layer. In the numerical analysis, we examined an influence of the dielectric circular cylinder along a middle layer by using the energy distribution and complex propagation constants at the first stop band region compared with hollow dielectric cylinder. In addition, we also investigated the influence of dielectric structure with equivalence cross section compared with dielectric cylinders, and clarified an influence of dielectric structures in the middle layer by energy distribution analysis for TE0 mode.

Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS techniques) are strongly required in various applications. Both interconnection delays and clock skews have a large impact on circuit performance implemented onto FPGA, which indicates the need for floorplan-driven FPGA-HLS algorithms considering them. To appropriately estimate interconnection delays and clock skews at HLS phase, a reasonable model to estimate them becomes essential. In this paper, we demonstrate several experiments to characterize interconnection delays and clock skews in FPGA and propose novel estimate models called “IDEF” and “CSEF”. In order to evaluate our models, we integrate them into a conventional floorplan-driven FPGA-HLS algorithm. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 22% compared with conventional approaches.

Visual tracking has been studied for several decades but continues to draw significant attention because of its critical role in many applications. Recent years have seen greater interest in the use of correlation filters in visual tracking systems, owing to their extremely compelling results in different competitions and benchmarks. However, there is still a need to improve the overall tracking capability to counter various tracking issues, including large scale variation, occlusion, and deformation. This paper presents an appealing tracker with robust scale estimation, which can handle the problem of fixed template size in Kernelized Correlation Filter (KCF) tracker with no significant decrease in the speed. We apply the discriminative correlation filter for scale estimation as an independent part after finding the optimal translation based on the KCF tracker. Compared to an exhaustive scale space search scheme, our approach provides improved performance while being computationally efficient. In order to reveal the effectiveness of our approach, we use benchmark sequences annotated with 11 attributes to evaluate how well the tracker handles different attributes. Numerous experiments demonstrate that the proposed algorithm performs favorably against several state-of-the-art algorithms. Appealing results both in accuracy and robustness are also achieved on all 51 benchmark sequences, which proves the efficiency of our tracker.

In this paper, we describe an improvement of integer factorization of k RSA moduli Ni=piqi (1≤i≤k) with implicit hints, namely all pi share their t least significant bits. May et al. reduced this problem to finding a shortest (or a relatively short) vector in the lattice of dimension k obtained from a given system of k RSA moduli, for which they applied Gaussian reduction or the LLL algorithm. In this paper, we improve their method by increasing the determinant of the lattice obtained from the k RSA moduli. We see that, after our improvement, May et al.'s method works smoothly with higher probability. We further verify the efficiency of our method by computer experiments for various parameters.

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480µW under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055mm2 chip area only.

Increasing demand in data-traffic has been addressed over the last few years. It is expected that the data-traffic will present the significant part of the total backbone traffic. Accordingly, much more transmission systems will be required to support this growth. A free space optic (FSO) communication is the greatest promising technology supporting high-speed and high-capacity transport networks. It can support multi Gbit/s for few kilometers transmission distance. The benefits of an FSO system are widespread, low cost, flexibility, immunity to electromagnetic field, fast deployment, security, etc. However, it suffers from some drawbacks, which limit the deployment of FSO links. The main drawback in FSO is the degradation in the signal quality because of atmospheric channel impairments. In addition, it is high sensitive for illumination noise coming from external sources such as sun and lighting systems. It is more benefit that FSO and mmWave are operating as a complementary solution that is known as hybrid FSO/mmWave links. Whereas the mmWave is susceptible to heavy rain conditions and oxygen absorption, while fog has no particular effect. This paper will help to better understand the FSO and mmWave technologies and applications operating under various atmospheric conditions. Furthermore, in order to improve the system performance and availability, several modulation schemes will be discussed. In addition to, the hybrid FSO/mmWave with different diversity combining techniques are presented.

In this paper, we propose improved methods of liquid-phase detection of biological targets utilizing magnetic markers and a high-critical-temperature superconducting quantum interference device (SQUID). For liquid-phase detection, the bound and unbound (free) markers are magnetically distinguished by using Brownian relaxation of free markers. Although a signal from the free markers is zero in an ideal case, it exists in a real sample on account of the aggregation and precipitation of free markers. This signal is called a blank signal, and it degrades the sensitivity of target detection. To solve this problem, we propose improved detection methods. First, we introduce a reaction field, Bre, during the binding reaction between the markers and targets. We additionally introduce a dispersion process after magnetization of the bound markers. Using these methods, we can obtain a strong signal from the bound markers without increasing the aggregation of the free markers. Next, we introduce a field-reversal method in the measurement procedure to differentiate the signal from the markers in suspension from that of the precipitated markers. Using this procedure, we can eliminate the signal from the precipitated markers. Then, we detect biotin molecules by using these methods. In an experiment, the biotins were immobilized on the surfaces of large polymer beads with diameters of 3.3 µm. They were detected with streptavidin-conjugated magnetic markers. The minimum detectable molecular number concentration was 1.8×10-19 mol/ml, which indicates the high sensitivity of the proposed method.

In the paradigm of network coding, when the network topology information cannot be utilized completely, random linear network coding (RLNC) is proposed as a feasible coding scheme. But since RLNC neither considers the global network topology nor coordinates codings between different nodes, it may not achieve the best possible performance of network coding. Hence, the performance analysis of RLNC is very important for both theoretical research and practical applications. Motivated by a fact that different network topology information can be available for different network communication problems, we study and obtain several upper and lower bounds on the failure probability at sink nodes depending on different network topology information in this paper, which is also the kernel to discuss some other types of network failure probabilities. In addition, we show that the obtained upper bounds are tight, the obtained lower bound is asymptotically tight, and we give the worst cases for different scenarios.

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mVpp, and so we successfully reduced the required read bitline signal from 250 to 70 mVpp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

In this study, a well-shaped microelectrode array (MEA) for fabricating a high-density complementary metal-oxide semiconductor amperometric electrochemical sensor array was designed and verified. By integrating an auxiliary electrode with the well-shaped structure of the MEA, the footprint was reduced and high density and high resolution were also achieved. The results of three-dimensional electrochemical simulations confirmed the effectiveness of the proposed MEA structure and possibility of increasing the density to four times than that achieved by the conventional two-dimensional structure.

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

Distributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.