A unified model for frequency-dependent characteristics of transconductance and output resistance is presented that incorporates the dynamics of quasi-Fermi levels. Using this model, multiple-frequency dispersion and pulse-narrowing phenomena in GaAs MESFETs are demonstrated based on the drift-diffusion transport theory and a Schockley-Read-Hall-type deep trap model, where rate equations for multiple trapping processes are analyzed self-consistently. It is shown that the complex frequency dependence is due to both spatial and temporal effects of multiple traps.

The structural necessary and sufficient condition for "the transition-liveness means the place-liveness and vice-versa" of a subclass NII of general Petri nets is given as "the place and transition live Petri net, or PTL net, ÑII". Furthermore, "the one-token-condition Petri net, or OTC net, II" which means that every MSDL (minimal structural deadlock) is "transition and place live" under at least one initial token, i.e., II is "transition and place live" under the above initial marking. These subclasses NII, ÑII( NII), and II(ÑII) are almost the general Petri nets except at least one MSTR(minimal structural trap) and at least one pair of "a virtual MSTR or a virtual STR" and "a virtual MSDL" of an MBTR (minimal behavioral trap) in connection with making an MSDL transition-live.

An automatic tap assignment method in sub-band adaptive filter is proposed in this letter. The number of taps of the adaptive filter in each band is controlled by the mean-squared error. The numbers of taps increase in the bands which have large errors, while they decrease in the bands having small errors, until residual errors in all the bands become the same. In this way, the number of taps in a band is roughly proportional to the length of the impulse response of the unknown system in this band. The convergence rate and the residual error are improved, in comparison with existing uniform tap assignment. Effectiveness of the proposed method has been confirmed through computer simulation.

The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issuse regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a 1.5-V supply voltage, a 106-synapse neural network capability, and a 0.5-µm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of 1.37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

First, a number of issues pertaining to analog VLSI implementation of Backpropagation (BP) and Deterministic Boltzmann Machine (DBM) learning algorithms are clarified. According to the results from software simulation, a mismatch between the activation function and derivative generated by independent circuits degrades the BP learning performance. The perfomance can be improved, however, by adjusting the gain of the activation function used to obtain the derivative, irrespective of the original activation function. Calculation errors embedded in the circuits also degrade the learning preformance. BP learning is sensitive to offset errors in multiplication in the learning process, and DBM learning is sensitive to asymmetry between the weight increment and decrement processes. Next, an analog VLSI architecture for implementing the algorithms using common building block circuits is proposed. The evaluation results of test chips confirm that synaptic weights can be updated up to 1 MHz and that a resolution exceeding 14 bits can be attained. The test chips successfully perform XOR learning using each algorithm.