The overall performance of P2P-based file sharing applications is becoming increasingly important. Based on the Adaptive Resource-based Probabilistic Search algorithm (ARPS), which was previously proposed by the authors, a novel probabilistic search algorithm with QoS guarantees is proposed in this letter. The algorithm relies on generating functions to satisfy the user's constraints and to exploit the power-law distribution in the node degree. Simulation results demonstrate that it performs well under various P2P scenarios. The proposed algorithm provides guarantees on the search performance perceived by the user while minimizing the search cost. Furthermore, it allows different QoS levels, resulting in greater flexibility and scalability.

We propose a new stopping criterion for decoding LDPC codes which consists of a measure of decoder behaviors and a decision rule to predict decoding failure. We will show that the proposed measure, the number of satisfied check nodes, does not need (or minimizes) additional complexity, and the decision rule is efficient and more importantly channel independent, which was not possible in the previous work.

The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.

We describe a sub 100-mW H.264 MP@L4.1 integer-pel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 19201080 pixels at 30 fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90 nm CMOS design rule. Core size is 2.52.5 mm2. One core supports one-reference-frame and dissipates 48 mW at 1 V. Two core configuration consumes 96 mW for two-reference-frame search.

Conventional narrowband interference (NBI) rejection algorithms often assumed perfect pseudo-noise (PN) code synchronization. The functions of NBI rejection and code tracking are performed separately and independently by an adaptive filter and a code tracking loop, respectively. This paper presents two new receiver structures for direct sequence spread spectrum (DS/SS) systems, one operates in coherent mode and the other operates in noncoherent mode. Both receivers are designed to suppress NBI and minimize tracking jitter. Numerical results show that the proposed coherent receiver performs as good as the conventional receiver that uses an LMS NBI rejection filter with zero tracking jitter. The noncoherent receiver, when compared with the coherent one, suffers less than 3 dB degradation for bit error probability smaller than 10-3.

In this paper, we propose δ-similar elimination to improve the search performance of multiobjective evolutionary algorithms in combinatorial optimization problems. This method eliminates similar individuals in objective space to fairly distribute selection among the different regions of the instantaneous Pareto front. We investigate four eliminating methods analyzing their effects using NSGA-II. In addition, we compare the search performance of NSGA-II enhanced by our method and NSGA-II enhanced by controlled elitism.

Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.

The paper presents a novel approach to estimate the performance of MPI collective communications. Our objective is to help researchers to make appropriate decisions on their message-passing applications. For each collective communication, we attempt to apply LogGP and P-LogP standard point-to-point models. The resulted models are compared with the empirical data in order to identify the most suitable for performance characterization of collective operations. For the communications on large clusters with large size messages, the network contention problem can significantly affect the performance. Hence, to reduce the relative gap between the prediction and the measured runtime, the contention issue is also modeled, by a queuing theory analysis method, and taken in account with the total performance estimation. The experiments performed on a cluster which consists of 64 processors interconnected by Gigabit Ethernet network show encouraging results. For any collective operation, given a number of processors and a range of message sizes, there is at least one model that predicts the performance precisely. We could achieve a gap between the predicted and the measured run-time around 15%. Thus, by handling the contention problem, we could reduce around 80% of the relative gap.

In order to estimate fast time-varying channels exactly, the Inter-Carrier Interference (ICI) caused by time-varying fading channels in Orthogonal Frequency Division Multiplexing (OFDM) systems is analyzed based on the Basis Expansion Model (BEM). A channel estimation and ICI cancellation algorithm with low complexity is proposed. A special pilot sequence is designed to minimize the cost of computing the channel state information in the proposed algorithm. Based on the property of channel frequency impulse matrix, the ICI can be canceled iteratively in frequency domain. The complexity of the algorithm is analyzed theoretically. Through simulation, the algorithm is shown to be effective in estimating channel state information and in cancelling ICI.

We propose a new approach to personal identification using derived vectorcardiogram (dVCG). The dVCG was calculated from recorded ECG using inverse Dower transform. Twenty-one features were extracted from the resulting dVCG. To analyze the effect of each feature and to improve efficiency while maintaining the performance, we performed feature selection using the Relief-F algorithm using these 21 features. Each set of the eight highest ranked features and all 21 features were used in SVM learning and in tests, respectively. The classification accuracy using the entire feature set was 99.53 %. However, using only the eight highest ranked features, the classification accuracy was 99.07 %, indicating only a 0.46 % decrease in accuracy compared with the accuracy achieved using the entire feature set. Using only the eight highest ranked features, the conventional ECG method resulted in a 93 % recognition rate, whereas our method achieved >99 % recognition rate, over 6 % higher than the conventional ECG method. Our experiments show that it is possible to perform a personal identification using only eight features extracted from the dVCG.

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 µm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 µm Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 µm standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstcase design environment improves optimization speed by 29.61-32.01% compared to that of the conventional worstcase optimization. The new statistical interconnect worstcase design environment accurately predicts the worstcase and bestcase corners of non-normal distribution where conventional methods cannot do well.

A branch-and-bound algorithm (BB for short) is the most general technique to deal with various combinatorial optimization problems. Even if it is used, computation time is likely to increase exponentially. So we consider its parallelization to reduce it. It has been reported that the computation time of a parallel BB heavily depends upon node-variable selection strategies. And, in case of a parallel BB, it is also necessary to prevent increase in communication time. So, it is important to pay attention to how many and what kind of nodes are to be transferred (called sending-node selection strategy). In this paper, for the graph coloring problem, we propose some sending-node selection strategies for a parallel BB algorithm by adopting MPI for parallelization and experimentally evaluate how these strategies affect computation time of a parallel BB on a PC cluster network.

In the acoustic echo canceller (AEC), the step-size parameter of the adaptive filter must be varied according to the situation if double talk occurs and/or the echo path changes. We propose an AEC that uses a sub-adaptive filter. The proposed AEC can control the step-size parameter according to the situation. Moreover, it offers superior convergence compared to the conventional AEC even when the double talk and the echo path change occur simultaneously. Simulations demonstrate that the proposed AEC can achieve higher ERLE and faster convergence than the conventional AEC. The computational complexity of the proposed AEC can be reduced by reducing the number of taps of the sub-adaptive filter.

The present paper describes a method for the construction of a zero-correlation zone sequence set from a perfect sequence. Both the cross-correlation function and the side-lobe of the auto-correlation function of the proposed sequence sets are zero for phase shifts within the zero-correlation zone. These sets can be generated from an arbitrary perfect sequence, the length of which is the product of a pair of odd integers ((2n+1)(2k+1) for k ≥ 1 and n ≥ 0). The proposed sequence construction method can generate an optimal zero-correlation zone sequence set that achieves the theoretical bounds of the sequence member size given the size of the zero-correlation zone and the sequence period. The peak in the out-of-phase correlation function of the constructed sequences is restricted to be lower than the half of the power of the sequence itself. The proposed sequence sets could successfully provide CDMA communication without co-channel interference, or, in an ultrasonic synthetic aperture imaging system, improve the signal-to-noise ratio of the acquired image.

This letter proposes a motion information inferring scheme for multi-view video coding motivated by the idea that the aspect of motion vector between the corresponding positions in the neighboring view pair is quite similar. The proposed method infers the motion information from the corresponding macroblock in the neighboring view after RD optimization with the existing prediction modes. This letter presents evaluation showing that the method significantly enhances the efficiency especially at high bit rates.

We analyze the MAC performance of the IEEE 802.11 DCF and 802.11e EDCA in non-saturation condition where device does not have packets to transmit sometimes. We assume that a flow is not generated while the previous flow is in service and the number of packets in a flow is geometrically distributed. In this paper, we take into account the feature of non-saturation condition in standards: possibility of transmission performed without preceding backoff procedure for the first packet arriving at the idle station. Our approach is to model a stochastic behavior of one station as a discrete time Markov chain. We obtain four performance measures: normalized channel throughput, average packet HoL (head of line) delay, expected time to complete transmission of a flow and packet loss probability. Our results can be used for admission control to find the optimal number of stations with some constraints on these measures.

We describe an extension of the wideband direction-of-arrival (DOA) estimation method using a frequency-domain frequency-invariant beamformer (FDFIB). The technique uses the Matrix Pencil Method (MPM) instead of conventional methods based on the eigen-structure of the input covariance matrix. MPM offers excellent resolution compared to conventional methods.

This paper proposes an efficient systolic array construction method for optimal planar systolic design of the matrix multiplication. By connection network adjustment among systolic array processing element (PE), the input/output data are jumping in the systolic array for multiplication operation requirements. Various 2-D systolic array topologies, such as square topology and hexagonal topology, have been studied to construct appropriate systolic array configuration and realize high performance matrix multiplication. Based on traditional Kung-Leiserson systolic architecture, the proposed "Jumping Systolic Array (JSA)" algorithm can increase the matrix multiplication speed with less processing elements and few data registers attachment. New systolic arrays, such as square jumping array, redundant dummy latency jumping hexagonal array, and compact parallel flow jumping hexagonal array, are also proposed to improve the concurrent system operation efficiency. Experimental results prove that the JSA algorithm can realize fully concurrent operation and dominate other systolic architectures in the specific systolic array system characteristics, such as band width, matrix complexity, or expansion capability.

An orthonormal basis adaptation method for function approximation was developed and applied to reinforcement learning with multi-dimensional continuous state space. First, a basis used for linear function approximation of a control function is set to an orthonormal basis. Next, basis elements with small activities are replaced with other candidate elements as learning progresses. As this replacement is repeated, the number of basis elements with large activities increases. Example chaos control problems for multiple logistic maps were solved, demonstrating that the method for adapting an orthonormal basis can modify a basis while holding the orthonormality in accordance with changes in the environment to improve the performance of reinforcement learning and to eliminate the adverse effects of redundant noisy states.

This paper investigates the design curves of the class DE amplifier with the nonlinear shunt capacitances for any output Q and any grading coefficient m of the diode junction in the MOSFET. The design curves are derived by the numerical calculation using Spice. The results of this paper have two important meanings. Firstly, it is clarified that the nonlinearities of the shunt capacitances affect the design curves of the class DE amplifier, especially, for low output Q. Moreover, the supply voltage is a quite important parameter to design the class DE amplifier with the nonlinear shunt capacitances. Secondly, it is also clarified that the numerical design tool using Spice, which is proposed by authors, can be applied to the derivation of the design curves. This shows the possibility of the algorithm to be a powerful tool for the analysis of the class E switching circuits. The waveforms from Spice simulations denote the validity of the design curves.