Ubiquitous computing and the upcoming broadcast-and-communication convergence require networks that provide very complex services. In particular, networks are needed that can service several users or terminals at various times or places with various application-layer functions that can be changed at a high response speed by adding high-speed processing at the network edge. I present a query-transaction acceleration appliance that uses a dynamic reconfigurable processor (DRP) and enables high-speed stateful packet-by-packet self-reconfiguration to achieve that requirement. This appliance processes at high speeds, has flexible application layer functions that are changeable with a high-speed response, and uses direct packet I/O bypassing memory, hierarchical interconnection of processors, and stateful packet-by-packet self-reconfiguration. In addition, the DRP enables the fabrication of a compact and electric-power-saving appliance. I made a prototype and implemented several transport/application layer functions, such as TCP connection control, auto-caching of server files, uploading cache data for server, and selection/insertion/deletion/update of data for a database. In an experimental evaluation in which four kinds of query-transactions were continually executed in order, I found that the appliance achieved four functions changeable at a high response speed (within 1 ms), and a processing speed (2,273 transactions/sec.) 18 times faster than a PC with a 2-GHz processor.

For formal verification of large-scale digital circuits, a method using satisfiability checking of logic with equality and uninterpreted functions has been proposed. This logic, however, does not consider specific properties of functions or predicates at all, e.g. associative property of addition. In order to ease this problem, we introduce "equivalence constraint" that is a set of formulas representing the properties of functions and predicates, and check the satisfiability of formulas under the constraint. In this report, we show an algorithm for checking satisfiability with equivalence constraint and also experimental results.

Multiple sequence alignment problems in computational biology have been focused recently because of the rapid growth of sequence databases. By computing alignment, we can understand similarity among the sequences. Many hardware systems for alignment have been proposed to date, but most of them are designed for two-dimensional alignment (alignment between two sequences) because of the complexity to calculate alignment among more than two sequences under limited hardware resources. In this paper, we describe a compact system with an off-the-shelf FPGA board and a host computer for more than three-dimensional alignment based on dynamic programming. In our approach, high performance is achieved (1) by configuring optimal circuit for each dimensional alignment, and (2) by two phase search in each dimension by reconfiguration. In order to realize multidimensional search with a common architecture, two-dimensional dynamic programming is repeated along other dimensions. With this approach, we can minimize the size of units for alignment and achieve high parallelism. Our system with one XC2V6000 enables about 300-fold speedup as compared with single Intel Pentium4 2 GHz processor for four-dimensional alignment, and 100-fold speedup for five-dimensional alignment.

In this paper, we propose a new code set which has very low spectral peak to average ratio (SPAR) and good correlation properties for DS-UWB. The codes which have low SPAR are suitable for DS-UWB system which operates in UWB (3.110.4 GHz) because they can utilize more power than high SPAR codes can do. And, in order to reduce inter symbol interference (ISI) and inter piconet interferences, the codes which have good auto- and cross-correlation properties must be used. In this paper, we propose three items; (1) a new code generation method which can generate good SPAR and auto-correlation codes, (2) code selection criteria, and (3) a code set, which has been selected according to the proposed selection criteria. The proposed code set has SPAR reduced about 0.22 dB and GMF improved by 30% compared to the previous code set while it is maintaining almost same cross-correlation properties. Each code of the proposed code set, therefore, has gained 1.43 dB SIR on an average compared to that of the previous code set.

In this paper, we describe a method of applying Collaborative Filtering with a Machine Learning technique to predict users' preferences for clothes on online shopping malls when user history is insufficient. In particular, we experiment with methods of predicting missing values, such as mean value, SVD, and support vector regression, to find the best method and to develop and utilize a unique feature vector model.

Most learning-based super-resolution methods neglect the illumination problem. In this paper we propose a novel method to combine blind single-frame super-resolution and shadow removal into a single operation. Firstly, from the pattern recognition viewpoint, blur identification is considered as a classification problem. We describe three methods which are respectively based on Vector Quantization (VQ), Hidden Markov Model (HMM) and Support Vector Machines (SVM) to identify the blur parameter of the acquisition system from the compressed/uncompressed low-resolution image. Secondly, after blur identification, a super-resolution image is reconstructed by a learning-based method. In this method, Logarithmic-wavelet transform is defined for illumination-free feature extraction. Then an initial estimation is obtained based on the assumption that small patches in low-resolution space and patches in high-resolution space share a similar local manifold structure. The unknown high-resolution image is reconstructed by projecting the intermediate result into general reconstruction constraints. The proposed method simultaneously achieves blind single-frame super-resolution and image enhancement especially shadow removal. Experimental results demonstrate the effectiveness and robustness of our method.

In this study, a wideband 3/4 elliptical ring patch operating millimeter wave band is proposed. Using this structure, the patch antenna is designed for circular polarization and wide-band operation at about 32.1-40 GHz for millimeter wave communication. Simulated and measured results for main parameters such as voltage standing wave ratio (VSWR), impedance bandwidth, axial ratio, radiation patterns and gains are also discussed. The study shows that modeling of such antennas, with simplicity in designing and feeding, can well meet the requirements of millimeter-wave wireless communication systems.

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current efficiency. Simulation results of a 0.5-V 100-kHz 5th-order Chebyshev filter based on the proposed OTA in a 0.18 µm CMOS process indicate SNR and SFDR of 68 dB and 63 dB (at 50 kHz+55 kHz) respectively. The filter consumes total power consumption of 60 µW.

We experimentally demonstrated polarization-mode dispersion (PMD) compensation by distributing polarizers with only 1 degree of freedom (DOF) along the transmission line. The average power penalty was measured to be 0.4 dB by inserting four compensators, where average differential group delay was 47% of bit period.

Recently, many studies reported various advanced e-Health service systems in patient care monitoring utilizing sensor networks and questionnaire systems. We propose an informant driven e-Health service system for the identification of heart rate related mental stress factors with a simple operation of informant-client model. Through performance analysis, we show that the proposed system is a cost-effective stress identification system applicable to mobile wireless networks.

Wireless content sharing where peers share content and services via wireless access networks requires user contributions, as in fixed P2P content sharing. However, in wireless access environments, since the resources of mobile terminals are strictly limited, mobile users are not as likely to contribute as ones in fixed environments. Therefore, incentives to encourage user contributions are more significant in wireless access environments. Although an incentive service differentiation architecture where the content transfer rate is adjusted according to the contributions of each downloading user has been already proposed for fixed P2P, it may not work well in wireless access environments because several factors effect wireless throughput. In this paper, we propose a novel architecture for contribution-based transfer-rate differentiation using wireless quality of service (QoS) techniques that motivates users to contribute their resources for wireless content sharing. We also propose a radio resource assignment method for our architecture. Computer simulations and game-theoretic calculations validate our architecture.

This paper proposes a simple, efficient method that, based on increasing the differences between two neighboring pixels, losslessly embeds a message into a host image. The point at which the number of pixel differences in the image is at a maximum is selected to embed the message. The selected difference is increased by 1 or left unchanged if the embedded bit is "1" or "0", respectively. On the other hand, differences larger than the selected difference are increased by 1. Increasing a difference is done by adding 1 to or subtracting 1 from the pixel if its value is larger or smaller than its preceding pixel, respectively. Experimental results show that the proposed method can achieve a high payload capacity while the image distortion of the stego-image remains minimal.

Design automation of LCD driver circuits is not sophisticatedly established. Display fineness of an LCD panel depends on a performance metric, ratio of pixel voltage to video voltage (RPV). However, there are several other important metrics, such as area, and the best circuit cannot be decided uniquely. This paper proposes a design automation technique for a LCD column driver to provide several circuit design results with different performance so that designers can select an appropriate design among them. The proposed technique is evaluated with an actual design data, and experimental results show that the proposed method successfully performs technology migration by transistor sizing. Also, the proposed technique is experimentally verified from points of solution quality and computational time.

Normalization transform is known to be very useful for finding the overall trend of time-series data since it enables finding sequences with similar fluctuation patterns. Previous subsequence matching methods with normalization transform, however, would incur index overhead both in storage space and in update maintenance since they should build multiple indexes for supporting query sequences of arbitrary length. To solve this problem, we adopt a single-index approach in the normalization-transformed subsequence matching that supports query sequences of arbitrary length. For the single-index approach, we first provide the notion of inclusion-normalization transform by generalizing the original definition of normalization transform. To normalize a window, the inclusion-normalization transform uses the mean and the standard deviation of a subsequence that includes the window while the original transform uses those of the window itself. Next, we formally prove the correctness of the proposed normalization-transformed subsequence matching method that uses the inclusion-normalization transform. We then propose subsequence matching and index-building algorithms to implement the proposed method. Experimental results for real stock data show that our method improves performance by up to 2.52.8 times compared with the previous method.

For coherent detection, decoding Orthogonal Space-Time Block Codes (OSTBC) requires full channel state information at the receiver, which basically is obtained by channel estimation. However, in practical systems, channel estimation errors are inevitable and may degrade the system performance more as the number of antennas increases. This letter shows that, using fewer receive antennas can enhance the performance of OSTBC systems in presence of channel estimation errors. Furthermore, a novel adaptive receive antenna selection scheme, which adaptively adjusts the number of receive antennas, is proposed. Performance evaluation and numerical examples show that the proposed scheme improves the performance obviously.

Numerical function generators (NFGs) realize arithmetic functions, such as ex,sin(πx), and , in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

The clonal selection algorithm (CS), inspired by the basic features of adaptive immune response to antigenic stimulus, can exploit and explore the solution space parallelly and effectively. However, antibody initialization and premature convergence are two problems of CS. To overcome these two problems, we propose a chaotic distance-based clonal selection algorithm (CDCS). In this novel algorithm, we introduce a chaotic initialization mechanism and a distance-based somatic hypermutation to improve the performance of CS. The proposed algorithm is also verified for numerous benchmark traveling salesman problems. Experimental results show that the improved algorithm proposed in this paper provides better performance when compared to other metaheuristics.

Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This paper proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load model.

We describe a way to write state machines inductively. The proposed method makes it possible to use the standard techniques for proving theorems on inductive types to verify that state machines satisfy invariant properties. A mutual exclusion protocol using a queue is used to exemplify the proposed method.

This paper presents a self-reconfigurable adaptive FIR filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, advantages of configuration time allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for realization and autonomous adaptation of FIR filters, and processes the optimal digital signal processing algorithms, which are the low-pass, band-pass and high-pass filter algorithms with various frequencies, for noise removal operations. The proposed stand-alone self-reconfigurable system using Xilinx Virtex4 FPGA and Compact-Flash memory shows the improvement of configuration time and flexibility by using the dynamic partial reconfiguration techniques.