Net-Oriented Analysis and Design (NOAD) is defined as three items: (1) Various nets are utilized as an effective modeling method. (2) Inter-relationships among verious nets are determined. (3) Verification or analysis methods for nets are provided and they are implemented based on the mathematical theory, that is Net theory. Very few methods have been presented to satisfy these three items. For example, the Real-Time SA method covers item (1) only. The Object-Oriented Analysis and Design method (OOA/OOD) covers items (1) and (2). NOAD can be regarded as an extension to OOA/OOD. This paper discusses how effectively various nets have been used in actual software development support metnods and tools and evaluates such several methods and tools from the NOAD viewpoint.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

An automatic macrocell generator has been developed and applied to the analog layout of SC and active-RC filters. The generator consists of a process independent generation procedure, a leafcell library, and a circuit description of the leafcells. The unit element arrays of the whole filter are generated together to minimize the array height of the entire filter macrocell, so that the area of the generated filter is as small as that of a manually laid out filter. Three SC filters and one active-RC filter were designed and fabricated by 1.5-µm CMOS technology, that successfully yielded an S/N ratio of more than 70 dB with a quick turn around time.

This paper describes a VLSI processor architecture designed for a back-propagation accelerator. Three techniques are used to accelerate the simulation. The first is a multi-processor approach where a neural network simulation is suitable for parallel processing. By constructing a ring network using several processors, the simulation speed is multiplied by the number of the processors. The second technique is internal parallel processing. Each processor contains 4 multipliers and 4 ALUs that all work in parallel. The third technique is pipelining. The connections of eight functional units change according to the current stage of the back-propagation algorithm. Intermediate data is sent from one functional unit to another without being stored in extra registers and data is processed in a pipeline manner. The data is in 24-bit floating point format (18-bit mantissa and 6-bit oxponent). The chip has about 88,000 gates, including microcode ROM for processor control, the processor is designed using 0.8-µm CMOS gate arrays, and the estimated performance at 40 MHz is 20 million connection updates per second (MCUPS). For a ring network with 4 processors, performance can be enhanced up to 90 MCUPS.

We propose a hierarchical multi-layer global router for Sea-Of-Gates VLSI's, which is different from the conventional global routers, in that routing and layering are executed simultaneously. The main problems to be solved in the global routing for a multi-layer VLSI are which wire segments are laid out on upper layers and how they are connected to terminals located on lower layers. The main objective is to minimize the maximum of local congestions of all layers. We solve these problems in a hierarchical manner by routing from upper layers to lower layers.

This paper deals with the sub-problems of generating a mask pattern from the logical description of a large-scale CMOS circuit. The large-scale layout can be generated in divide-and-conquer style: divide a given circuit into a set of sub-circuits, generate the layout of each sub-circuit, and merge the resulting layouts to create the whole layout. This paper proposes a layout synthesis algorithm for a sub-circuit with physical constraints for the synthesis scheme above. The physical constraints considered here are the relative placement of logic cells (sets of logic gates) and the routing constraint based on the costs of wiring layers and vias. These constraints will be given by the global optimizer in a two-dimensional layout synthesis routine, and they should be kept at the subsequent one-dimensional layout synthesis for a sub-circuit. The latter is also given for enhancing the circuit performance by limiting the usage of wiring layers and vias for special net such as a clock net. The placement constraint is maintained using PQ-tree, a tree structure representing a set of restricted permutations of elements. One-dimensional layout synthesis determines the placement of transistors by the enhanced pairwise exchanging method under the PQ-tree representation. The routing constraints is considered in the newly developed line-search routing method using a cost-based searching. Experimental results for practical standard cells, including up to 200 transistors, prove that the algorithms can produce the layouts comparable to handcrafted cells. Also on a two-dimensional layout synthesis using the algorithms, the results for benchmark circuits of Physical Design Workshop 1989, i.e., MCNC benchmark circuits, are superior to the best results exhibited at Design Automation Conference 1990.

This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.

This paper describes a programming system, K-NET for the development of control software for flexible manufacturing systems composed of robots, numerically-controlled machines, transfer machines and automatic storage/retrieval systems. K-NET is based on a high-level Petri net which makes it simple to express operational functions such as synchronization, interlock and concurrence in sequence control. Petri net in K-NET is colored one in which tokens have attributes, and timed one which can provide a notion of stochastic time. K-NET provides many kinds of boxes having specific functions, and gates specified the firing condition and the token flow control with IF-THEN rules. On the other hand, procedural language can be also used for information processing. K-NET can support all development stages including general design, detailed design, programming and testing. K-NET has an editor to input control specifications expressed with Petri net; a simulator to verify edited specifications; a generator to convert the net to C source programs for a computer or to ladder diagrams for a programmable controller; a reporter to print control specifications; and a monitor to display controller status in real-time. K-NET has been used in the development of control software for an automated guided vehicle system, and results show a 2/3rds cost-saving over development with conventional methods in which only procedural language is used.

This paper describes the integration of a qualitative method and a quantitative method by Bottleneck Diagnosis/Improvement Expert Systems for Synchronized queueing network (BDES-S and BIES-S). On the basis of qualitative reasoning, BDES-S can carry out parameter tuning in order to diagnose and improve bottlenecks of synchronized queueing networks. BDES-S can produce several alternative qualitative improvement plans for one bottleneck server. BIES-S can produce quantitative improvement equations for each qualitative improvement plan. Our method using BDES-S and BIES-S can integrate both quantitative and qualitative methods for parameter tuning on complicated queueing synchronized networks.

In this paper, we analyze a photodetection process of new kind theoretically, which transforms a coherent state of light so as to lead to nonstandard property, namely, sub-Poissonian distribution of its output photoelectron during its photodetection process. The properties of the photoelectron distribution are studied used as preamplifiers of both direct-detection and homodyne detection cases.

This letter proposes an improvement of the equivalent source method in order to give an accurate solution for the scattering of an electromagnetic plane wave by a conducting cylinder with edges.

The mode partition noise of 1.3µm distributed feedback laser diodes (DFB LD's), which is induced by the externally reflected light, is studied experimentally and numerically. The mode partition noise is evaluated by the k-value. It is observed that the mode parition noise monotonically increases with the DC bias current when the reflected light affects DFB LD's and the DC bias current is above the threshold current. From the dependence of the k-value on the external power reflection coefficient, it is observed that the k-value dramatically increases when the external power reflection coefficient is above a value which differs from LD to LD. This is closely related to the fact that the tolerance to the externally reflected light depends on the threshold gain difference between the main mode and the dominant side mode.

Recently most of the singularities of the equivalent edge currents for flat plates were eliminated by the authors using the paths of most rapid phase variation. A unique direction on the plate was determined for given incidence and observer. This paper extends this method for arbitrary angle wedges and presents the new expressions of the equivalent edge currents. The resultant expressions are valid for any incidence and observation aspects and have no false singularities. Diffraction patterns and radar cross sections of 3-D objects composed of wedges are calculated by using these currents. They show good agreements with experimental data or the results by the other methods.

This paper first discusses the software reusability-based development process in a lifecycle and reusable objects modification process called differentiation. Next, the supporting environment is described. Both the method and the environment allow developers to carry out requirement definitions, specification and implementation in a reusable way. Some quantitative evaluations are given about how productivity and quality have been improved by using this method and environment, based on a number of case studies made on development projects. Reusability has been largely improved by differential specification, and adjustment method and a direct transformation capability.

A specification formalism for business application software is presented. Our approach is to investigate specification documents which are actually used in development projects of business applications in banking, insurance, and government systems. Since the specification documents are prepared mainly for users' review for the developing software, the representation of the documents is designed to be easy to understand for users, only in business terminology without losing a certain level of formality. Also, to avoid redundancy of the specification, there are some implicit assumptions in the specification. We have analyzed some commonality of these assumptions hidden in specification documents and are trying to construct a language by formalizing the underlying system model.

This paper describes a new metric for evaluating the cost effectiveness of software reviews. The proposed metric is based on the degree to which costs needed for detecting all faults from software are reduced by software reviews in a project. The metric can be interpreted as combining two conventional metrics proposed by Fagan (1976) and Collofello and Woodfield (1989). As the proposed metric is normalized by virtual testing cost, we can compare the values of it among any different kind of projects. Using an experimental evaluation of the conventional metrics and the proposed metric for data collected in an industrial environment, we show the validity and usefulness of the proposed metric. In addition, we present a method to estimate a value of the proposed metric by using only the values which can be computed during the software reviews.

A novel harmonic retrieval algorithm is proposed in this paper based on Hopfield's neural network. Frequencies can be retrieved with high accuracy and high resolution under low signal to noise ratio (SNR). Amplitudes and phases in harmonic signals can also be estimated roughly by an energy constrained linear projection approach as proposed in the algorithm. Only no less than 2q neurons are necessary in order to detect harmonic siglnals with q different frequencies, where q denotes the number of different frequencies in harmonic signals. Experimental simulations show fast convergence and stable solution in spite of low signal to noise ratio can be obtained using the proposed algorithm.

In case of the system identification problem, such as an echo canceller, estimated impulse response obtained by the frequency-domain adaptive filter based on the circular convolution has estimation error because the unknown system is based on the linear convolution in the time domain. In this correspondence, we consider a sufficient condition to reduce the estimation error.

In this paper, a new M-estimation technique for the linear prediction analysis of speech is proposed. Since in the conventional linear prediction (CLP) method the obtained estimates are very much affected by the large amplitude residual parts, in the proposed method we use a loss function which assigns large weighting factor for small amplitude residuals and small weighting factor for large amplitude residuals which is for instance caused by the pitch excitations. The loss function is based on the assumption that the residual signal has an independent and identical t-distribution t(α) with α degrees of freedom. The efficiency of this new estimator depends on α. When α=, we get the CLP method. When the proposed method with small α is applied to the problems of estimating the formant frequencies and bandwidths of the synthetic speech by finding the roots of the prediction polynomial, we can achieve a more accurate and a smaller standard deviation (SD) estimate than that with large α. When the signal is very spiky, the proposed method can ahieve more efficient and accurate estimates than that with robust linear prediction (RBLP) method. The loss function is modified in the similar manner as the autocorrelation method. The solution is calculated by the Newton-Raphson iteration technique. The simulation results show that only few iterations are needed to reach a stationary point, the stationary point is always a local minimum and the obtained prediction filter is always minimum phase. Preliminary experiments on the human speech data indicate that the obtained results are insensitive to the placement of the analysis window and a higher spectral resolution than the CLP and RBLP method can be achieved.

This paper describes the impact of EDFAs on AM/FM FDM subcarrier multiplexing (SCM) all-fiber video distribution (AFVD) systems. As AM/FM hybrid system using EDFAs which can simultaneously distribute 11 AM-TV channels and 50 FM-TV channels is proposed and discussed. 4-stage amplifier-branch transmission experiments are introduced. The construction and performance of a newly designed 50 channel FM tuner are also presented.