In this report we present all-optical switches and modulators based on the intersubband transition in semiconductor quantum wells. The use of InGaAs/AlAsSb coupled double quantum well structures is proposed to facilitate intersubband transitions in the optical-communication band, and to reduce the intersubband absorption recovery time from several picoseconds to a few hundred femtoseconds by utilizing enhanced electron-phonon scattering. Subpicosecond all-optical gating and modulation in coupled double quantum wells are observed using pump-probe experiments at optical-communication wavelengths. The results indicate that the intersubband transition in this structure is very useful for ultrafast all-optical switching devices.

This letter proposes a low-power tournament branch predictor, in which the number of accesses to the branch predictors (local predictor or global predictor) is reduced. Analysis results with Samsung Memory Compiler show that the proposed branch predictor reduces the power consumption by 24-45%, compared to the conventional tournament branch predictor, not requiring any additional storage arrays, not incurring any additional delay and never harming accuracy.

Recently, broadband access is widely spreading, and many broadband network E-commerce services are planned and developed. This article proposes a broadband online shop where a videoconferencing system is used to enable direct, face-to-face communication. It is important for a broadband online shop to understand what preference their customers want in order to provide them with more appropriate information. By using customer preferences, a salesclerk can have a serviceable conversation with few questions to his online customers. So, we are developing a visual Customer Relationship Management system (v-CRM system) that offers customer preferences to broadband network service such as broadband online shop. In this paper, we classify customer preferences, and describe three visualization methods that enable customer preferences to be intuitively understood quickly. We outline the v-CRM evaluation system and describe an experiment where we evaluated how accurately customer preferences can be recognized using these methods. The results show that v-CRM system is effective for understanding customer preferences.

In this paper, the optimal assignment problem which assigns cells in PCS (Personal Communication Service) to switches on ATM (Asynchronous Transfer Mode) network is investigated. The cost considered in this paper has two components: one is the cost of handoff that involves two switches, and the other is the cost of cabling. This problem assumes that each cell in PCS can be assigned to two switches in ATM network. This problem is modelled as dual-homing cell assignment problem, which is a complex integral linear programming (ILP) problem. Since finding an optimal solution of this problem is NP-hard, a hybrid method which combines several heuristics and a stochastic search method (based on a simulated annealing(SA) approach) is proposed to solve this problem. The solution method consists of three phases: Primary Assignment Decision Phase (PADP), Secondary Assignment Decision Phase (SADP) and Refinement Phase (RP). The PADP and SADP are used to find good initial assignment, then domain-dependent heuristics are encoded into perturbations of SA in Refinement Phase to improve the result. Simulation results show that the proposed hybrid method is robust for this problem.

This paper proposes an analytical model to demonstrate the benefit of data service in wireless networks using dynamic multi-channel scheme with channel de-allocation. The performance of a system providing buffers to voice calls to reduce the raised voice blocking probability caused by data contention is investigated. The effect of the cell dwell time and overlap area with adjacent cells on system performance are studied. All free channels are allocated to data users dynamically. For those data users using more than one channel, channels would be de-allocated for new requests, voice or data. Buffers are provided for voice calls to reduce the voice blocking probability caused by data packets contention. Handoff calls are given priority to be queued in the front of the buffer instead of providing guard channels to reduce their dropping probability. Meanwhile, the reneging time for new calls and the handoff dwell time for handoff calls are considered in our analysis to obtain an appropriate amount of buffer to voice. To compensate the blocking probability in data, guard channels are provided for data traffic. Numerical results show that the dynamic multi-channel scheme with possible de-allocation, compared with the single channel scheme, can enhance data traffic performance significantly in terms of the mean transmission time and blocking probability. A system providing an appropriate amount of buffer to voice traffic and giving priority to queued handoff calls can indeed reduce new call blocking probability and handoff call dropping probability. In addition, the proposed scheme can reduce the incomplete transmission probability of data packets.

In this paper, we analyzed the performance of dynamic resource allocation with channel de-allocation and buffering in cellular networks. Buffers are applied for data traffic to reduce the packet loss probability while channel de-allocation is exploited to reduce the voice blocking probability. The results show that while buffering data traffic can reduce the packet loss probability, it has negative impact on the voice performance even if channel de-allocation is exploited. Although the voice blocking probability can be reduced with large slot capacity, the improvement decreases as the slot capacity increases. On the contrary, the packet loss probability increases as the slot capacity increases. In addition to the mean value analysis, the delay distribution and the 95% delay of data packets are provided.

In this paper, we consider a location management scheme using Limited Pointer forwarding from Commonly visited sites (LPC) strategy for Personal Communication Services (PCS) networks. The Commonly Visited Site (CVS) is defined as a site in which a mobile user is found with high probability. A feature of the strategy is that it skips updating location information of the mobile user, provided that the mobile user moves within its CVSs. Such a strategy is expected to significantly reduce the location update cost. We evaluate the location management cost of the LPC scheme by employing a Continuous-Time Markov Chain (CTMC) model. We show that the LPC scheme can reduce the location management cost of a highly mobile user who is found in its CVS with high probability.

We have proposed a speculative selection function for adaptive routing, which uses idle cycles of the network physical links to exchange network information between nodes, thus helps to decide the best selection. Previous study on the mesh network showed that SSR gives message selection flexibility that improves network performance by balancing the network traffic in both global and local scopes. This paper evaluates the speculative selection function on 2D torus network with simulation. The simulation compares the network throughput and latency with various traffic patterns. The visualization graphs show how the speculative selection eliminates hotspots and disperses traffic in the global scope. The simulation results demonstrate that by using speculative selection, the network performance is increased by around 7%. Compared to the mesh network, the torus's version has smaller gain due to the high performance nature of the torus network.

Parallel memories increase memory bandwidth with several memory modules working in parallel and can be used to feed a processor with only necessary data. The Configurable Parallel Memory Architecture (CPMA) enables a multitude of access formats and module assignment functions to be used within a single hardware implementation, which has not been possible in prior embedded parallel memory systems. This paper focuses on address computation in CPMA, which is implemented using several configurable computation units in parallel. One unit is dedicated for each type of access formats and module assignment functions that the implementation supports. Timing and area estimates are given for a 0.25-micron CMOS process. The utilized resources are shown to be linearly proportional to the number of memory modules.

Traditional Web cache servers based on HTTP and ICP infrastructure tend to have higher hardware and management cost, have difficulty in availability, automatic and dynamic reconfiguration, and may have slow links to some users. We find that peer-to-peer technology can help solve these problems. The peer cache service (PCS) we proposed here leverages each peer's local cache, similar access patterns, fully distributed coordination, and fast communication channels to enhance response time, scale of cacheable objects, and availability. Moreover, incorporating goals and strategies such as making the protocol lightweight and mutually compatible with existing cache infrastructure, supporting mobile devices, undertaking dynamic three-level caching, and exchanging cache meta-information further improve the effectiveness and differentiate our work from other similar-at-first-glance P2P Web cache systems.

The alignment of biological sequences is a crucial tool in molecular biology and genome analysis. A wide variety of approaches has been proposed for multiple sequence alignment problem; however, some of them need prerequisites to help find the best alignment or some of them may suffer from the drawbacks of complexity and memory requirement so they can be only applied to cases with a limited number of sequences. In this paper, we view the multiple sequence alignment problem as an optimization problem and propose a heuristic-based genetic algorithm (GA) approach to solve it. The heuristic/GA hybrid yields better results than other well-known packages do. Experimental results are presented to illustrate the feasibility of the proposed approach.

In a Distributed Computing Systems (DCS) tasks submitted to it, are usually partitioned into different modules and these modules may be allocated to different processing nodes so as to achieve minimum turn around time of the tasks utilizing the maximum resources of the existing system such as CPU speed, memory capacities etc. The problem lies on how to obtain the optimal allocation of these multiple tasks by keeping in mind that no processing node is overloaded due to this allocation. This paper proposes an algorithm A*RS, using well-known A*, which aims to reduce the search space and time for task allocation. It aims at minimization of turn around time of tasks in the way so that processing nodes do not become overloaded due to this allocation. Our experimental results justify the claims with necessary supports by comparing it with the earlier algorithm for multiple tasks allocation.

Graph data in large scientific/engineering applications are often too massive to fit inside the computer's main memory. The resulting input/output (I/O) costs could be a major performance bottleneck. This paper proposes an extension to extant multilevel graph partitioning algorithms with improved I/O-efficiency. The input graph is envisioned as the union of disjoint blocks (subgraphs) of almost the same size. Each block is coarsened in turn. Recursive matching and contraction are the operations in this phase. All the coarsened blocks are then merged in an iterative manner in order to ensure that the resulting graph fits in the main memory. This graph is then treated with an in-core multilevel graph partitioning algorithm in the usual way. Our experimental results show that the larger graph size is, the more dependent on the I/O-efficiency the performance is. And our modification can easily partition very large graphs. It also exhibits considerable improvement in I/O-complexity.

In this paper we consider the Feedback-Guided Dynamic Loop Scheduling (FGDLS) method that was proposed by Bull. The method uses a feedback-guided mechanism to schedule a parallel loop within a sequential outer loop. The execution times and the scheduling bounds at a outer iteration are used to find the scheduling bound of the next outer iteration. In this way FGDLS achieves an optimal load balance. Two algorithms have been proposed so far by Tabirca et al. In this article we will review these two algorithms and will give a comparison between their performances.

This paper shows how to use sticker to construct solution space of DNA for the library sequences in the set-packing problem and the clique problem. Then, with biological operations, we propose DNA-based algorithms to remove illegal solutions and to find legal solutions for the set-packing and clique problems from the solution space of sticker. Any NP-complete problem in Cook's Theorem can be reduced and solved by the proposed DNA-based computing approach if its size is equal to or less than that of the set-packing problem. Otherwise, Cook's Theorem is incorrect on DNA-based computing and a new DNA algorithm should be developed from the characteristics of the NP-complete problem. Finally, the result to DNA simulation is given.

Scientific computations for diffusion equations and ANNs (Artificial Neural Networks) are data intensive tasks accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. Thus, this type of tasks naturally maps onto SIMD (Single Instruction Multiple Data stream) parallel processing with distributed memory. This paper proposes a high performance acceleration processor of which architecture is optimized for scientific computing using diffusion equations and ANNs. The proposed architecture includes a customized instruction set and specific hardware resources which consist of a control unit (CU), 16 processing units (PUs), and a non-linear function unit (NFU) on chip. They are effectively connected with dedicated ring and global bus structure. Each PU is equipped with an address modifier (AM) and 16-bit 1.5 k-word local memory (LM). The proposed processor can be easily expanded by multi-chip expansion mode to accommodate to a large scale parallel computation. The prototype chip is implemented with FPGA. The total gate count is about 1 million with 530, 432-bit embedded memory cells and it operates at 15 MHz. The functionality and performance of the proposed processor is verified with simulation of oil reservoir problem using diffusion equations and character recognition application using ANNs. The execution times of two applications are compared with software realizations on 1.7 GHz Pentium IV personal computer. Though the proposed processor architecture and the instruction set are optimized for diffusion equations and ANNs, it provides flexibility to program for many other scientific computation algorithms.

The multiplication of large spare matrices is a basic operation in many scientific and engineering applications. There exist some high-performance library routines for this operation. They are often optimized based on the target architecture. For a parallel environment, it is essential to partition the entire operation into well balanced tasks and assign them to individual processing elements. Most of the existing techniques partition the given matrices based on some kind of workload estimation. For irregular sparse matrices on PC clusters, however, the workloads may not be well estimated in advance. Any approach other than run-time dynamic partitioning may degrade performance. In this paper, we apply our super-programming approach to parallel large matrix multiplication on PC clusters. In our approach, tasks are partitioned into super-instructions that are dynamically assigned to member computer nodes. Thus, the load balancing logic is separated from the computing logic; the former is taken over by the runtime environment. Our super-programming approach facilitates ease of program development and targets high efficiency in dynamic load balancing. Workloads can be balanced effectively and the optimization overhead is small. The results prove the viability of our approach.

We describe the characteristics of all-optical switching schemes based on semiconductor optical amplifiers (SOAs), with particular emphasis on the role of the fast carrier dynamics. The SOA response to a single short pulse as well as to a data-modulated pulse train is investigated and the properties of schemes relying on cross-gain as well as cross-phase modulation are discussed. The possible benefits of using SOAs with quantum dot active regions are theoretically analyzed. The bandfilling characteristics and the presence of fast capture processes may allow to reach bitrates in excess of 100 Gb/s even for simple cross-gain modulation schemes.

Ultrahigh-speed all-optical label processing method is proposed and experimentally demonstrated. This processing method dramatically increases the label processing capability. Optical packet switch (OPS) systems and networks based on OPS nodes are applications of optical processing technologies. For the experiment, we constructed the world's first 40 Gbit/s/port OPS prototype with an all-optical label processor, optical switch, optical buffer, and electronic scheduler. Three-hop optical packet routing using OPS nodes was experimentally demonstrated with it, verifying the feasibility of OPS networks.

In this paper, we propose a statistical method of time synchronization for computer clocks that have precisely frequency-synchronized oscillators. This method not only improves the accuracy of time synchronization but also prevents degradation in the frequency stability of the precise oscillators when the errors in the measured time offsets between computer clocks caused by network traffic possess a Gaussian distribution. Improved accuracy of time synchronization is achieved by estimating the confidence interval of the measured time offsets between the clocks. Degradation in frequency stability is prevented by eliminating unnecessary time correction for the computer clock, because time correction generally causes changes in the frequency accuracy and stability of the precise oscillators. To eliminate unnecessary time correction, our method uses an extended hypothesis test of the difference between the current mean and the mean at the last time adjustment to determine whether time correction is needed. Evaluation by simulating changes in the time offset of the existing ISDN clock synchronization system showed that this method achieves accurate time and stable frequency synchronization.