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13161-13180hit(20498hit)

  • Multi-Stage Unsupervised Learning for Multi-Body Motion Segmentation

    Yasuyuki SUGAYA  Kenichi KANATANI  

     
    PAPER-Image Recognition, Computer Vision

      Vol:
    E87-D No:7
      Page(s):
    1935-1942

    Many techniques have been proposed for segmenting feature point trajectories tracked through a video sequence into independent motions, but objects in the scene are usually assumed to undergo general 3-D motions. As a result, the segmentation accuracy considerably deteriorates in realistic video sequences in which object motions are nearly degenerate. In this paper, we propose a multi-stage unsupervised learning scheme first assuming degenerate motions and then assuming general 3-D motions and show by simulated and real video experiments that the segmentation accuracy significantly improves without compromising the accuracy for general 3-D motions.

  • Adaptive Rake Receiver with Sliding Window Linearly Constrained RLS Algorithm for Multipath Fading DS-SS CDMA System

    Shiunn-Jang CHERN  Chun-Hung SUN  Hsin-Pei LEE  

     
    PAPER-Wireless Communication Technology

      Vol:
    E87-B No:7
      Page(s):
    1970-1976

    An adaptive filtering algorithm based on the sliding window criterion is known to be very attractive for violent changing environments. In this paper, a new sliding window linearly constrained recursive least squares (SW-LC-RLS) algorithm based on the modified minimum mean squared error (MMSE) structure is devised for the RAKE receiver in direct sequence spread spectrum code-division multiple access (DS-SS CDMA) system over multipath fading channels, where the channel estimation scheme is accomplished at the output of adaptive filter. The proposed SW-LC-RLS algorithm has the advantage of having faster convergence property and tracking ability, and can be applied to the environments, where the narrowband interference is joined suddenly to the system, to achieve desired performance. Via computer simulation, we show that the performance, in terms of mean square errors (MSE), signal to interference plus noise ratio (SINR) and bit error rate (BER), is superior to the conventional LC-RLS and orthogonal decomposition-based LMS algorithms based on the MMSE structure.

  • Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification

    Hanxi ZHU  Ikuo YOSHIHARA  Kunihito YAMAMORI  Moritoshi YASUNAGA  

     
    PAPER-Biocybernetics, Neurocomputing

      Vol:
    E87-D No:7
      Page(s):
    1943-1952

    We have developed Multi-modal Neural Networks (MNN) to improve the accuracy of symbolic sequence pattern classification. The basic structure of the MNN is composed of several sub-classifiers using neural networks and a decision unit. Two types of the MNN are proposed: a primary MNN and a twofold MNN. In the primary MNN, the sub-classifier is composed of a conventional three-layer neural network. The decision unit uses the majority decision to produce the final decisions from the outputs of the sub-classifiers. In the twofold MNN, the sub-classifier is composed of the primary MNN for partial classification. The decision unit uses a three-layer neural network to produce the final decisions. In the latter type of the MNN, since the structure of the primary MNN is folded into the sub-classifier, the basic structure of the MNN is used twice, which is the reason why we call the method twofold MNN. The MNN is validated with two benchmark tests: EPR (English Pronunciation Reasoning) and prediction of protein secondary structure. The reasoning accuracy of EPR is improved from 85.4% by using a three-layer neural network to 87.7% by using the primary MNN. In the prediction of protein secondary structure, the average accuracy is improved from 69.1% of a three-layer neural network to 74.6% by the primary MNN and 75.6% by the twofold MNN. The prediction test is based on a database of 126 non-homologous protein sequences.

  • Routing and Re-Routing of Reliable Label Switched Paths with Variable Bandwidths in MPLS over Optical Networks

    Nagao OGINO  Hideaki TANAKA  

     
    PAPER-Optical Network Operation

      Vol:
    E87-B No:7
      Page(s):
    1834-1843

    Integration of the MPLS network and the optical mesh network is a promising approach to realize an efficient backbone network. Because large volumes of traffic incur damage from failure, survivability is important in the backbone network. In the MPLS over optical networks, a pair of primary LSP (Label Switched Path) and secondary LSP needs to be established on two optical link-disjoint routes assuming all single optical link failures. However, two link-disjoint routes in the MPLS layer may not correspond to two link-disjoint routes in the optical layer. Thus, a pair of primary and secondary LSPs should be routed considering link-disjointness in the optical layer. In the MPLS over optical networks, secondary LSPs can mutually share lightpath bandwidth if those secondary LSPs correspond to the primary LSPs that never fail simultaneously. Thus, routing of secondary LSPs should promote sharing of the lightpath bandwidth among the secondary LSPs. The primary and secondary LSPs with variable bandwidths should efficiently be packed into fewer lightpaths with a fixed bandwidth. Moreover, if all the LSPs accommodated in a lightpath can be re-routed to other lightpaths, this lightpath can then be released. By re-routing only secondary LSPs, unnecessary lightpaths may be released without disturbance of the conveyed traffic. This paper proposes an efficient routing scheme to establish primary and secondary LSPs with variable bandwidths through the MPLS over optical network. This routing scheme satisfies the above conditions. The bandwidth of each lightpath is efficiently utilized by this routing scheme, and the loss rate of LSP requests can be reduced. This paper also proposes an efficient re-routing scheme to remove secondary LSPs from selected lightpaths through which the efficiency of channel utilization in the optical links is increased, and the loss rate of LSP requests can be reduced as a result. Both the proposed routing and re-routing schemes are quantitatively evaluated and the effectiveness of those schemes is verified by computer simulation.

  • Active Anycast Technique that Achieves Capacity-Aware Load Balancing for Heterogeneous IP Networks

    Satoru OHTA  Toshiaki MIYAZAKI  

     
    PAPER-Internet

      Vol:
    E87-B No:7
      Page(s):
    2004-2012

    Real-world IP networks are heterogeneous in terms of server and link capacities. A sophisticated and comprehensive load balancing method is essential if we are to avoid congestion in the servers and links of heterogeneous networks. If such a method is not available, network throughput is limited by bottleneck servers or links. This paper proposes an anycast technique that achieves load balancing under heterogeneity. The proposed method well suits implementation on active networks. By taking advantage of the processing ability provided by active nodes, the method can decide packet routes flexibly on the basis of various criteria to realize a variety of load balancing schemes. Some of these schemes can successfully prevent the congestion of heterogeneous networks by tackling bottlenecks in both server and link capacities. The method is also advantageous given its light control load even when using many mirrored servers. Computer simulations confirm the effectiveness of these features.

  • An Algorithm for Detecting 3-Way Feature Interactions

    Shizuko KAWAUCHI  Tadashi OHTA  

     
    PAPER-Software Development Environment

      Vol:
    E87-B No:7
      Page(s):
    1910-1917

    This paper proposes an algorithm for detecting 3-way interactions. As far as the authors know, this is the first proposal ever made for a detection algorithm of 3-way interactions. In this paper, by analyzing examples, the mechanism of 3-way interactions is clarified and a detection algorithm of 3-way interactions is proposed. Namely the proposed detection algorithm is heuristic. To evaluate the algorithm, we implemented a detection system based on the proposed algorithm and applied it to 12 services, and 82 3-way interactions were detected. This shows the proposed algorithm is effective.

  • Robust VQ-Based Digital Watermarking for the Memoryless Binary Symmetric Channel

    Jeng-Shyang PAN  Min-Tsang SUNG  Hsiang-Cheh HUANG  Bin-Yih LIAO  

     
    LETTER-Image

      Vol:
    E87-A No:7
      Page(s):
    1839-1841

    A new scheme for watermarking based on vector quantization (VQ) over a binary symmetric channel is proposed. By optimizing VQ indices with genetic algorithm, simulation results not only demonstrate effective transmission of watermarked image, but also reveal the robustness of the extracted watermark.

  • Joint Frequency-Domain Equalization and Antenna Diversity Combining for Orthogonal Multicode DS-CDMA Signal Transmissions in a Frequency-Selective Fading Channel

    Takeshi ITAGAKI  Fumiyuki ADACHI  

     
    PAPER-Wireless Communication Technology

      Vol:
    E87-B No:7
      Page(s):
    1954-1963

    Orthogonal multicode direct sequence code division multiple access (DS-CDMA) has the flexibility in offering various data rate services. However, in a frequency-selective fading channel, the bit error rate (BER) performance is severely degraded since the othogonality among spreading codes is partially lost. In this paper, we apply frequency-domain equalization and antenna diversity combining, used in multi-carrier CDMA (MC-CDMA), to orthogonal multicode DS-CDMA in order to restore the code othogonality while achieving frequency and antenna diversity effect. It is found by computer simulations that the joint use of frequency-domain equalization and antenna diversity combining can significantly improve the BER performance of orthogonal multicode DS-CDMA in a frequency-selective fading channel.

  • VLaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation

    Suhyun KIM  Soo-Mook MOON  Kemal EBCIOLU  Erik ALTMAN  

     
    PAPER-Software Support and Optimization Techniques

      Vol:
    E87-D No:7
      Page(s):
    1712-1720

    For network computing on desktop machines, fast execution of Java bytecode programs is essential because these machines are expected to run substantial application programs written in Java. We believe higher Java performance can be achieved by exploiting instruction-level parallelism (ILP) in the context of Java JIT compilation. This paper introduces VLaTTe, a Java JIT compiler for VLIW machines that performs efficient scheduling while doing fast register allocation. It is an extended version of our previous JIT compiler for RISC machines called LaTTe whose translation overhead is low (i.e., consistently taking one or two seconds for SPECJVM98 benchmarks) due to its fast register allocation. VLaTTe adds the scheduling capability onto the same framework of register allocation, with a constraint for precise in-order exception handling which guarantees the same Java exception behavior with the original bytecode program. Our experimental results on the SPECJVM98 benchmarks show that VLaTTe achieves a geometric mean of useful IPC 1.7 (2-ALU), 2.1 (4-ALU), and 2.3 (8-ALU), while the scheduling/allocation overhead is 3.6 times longer than LaTTe's on average, which appears to be reasonable.

  • Multiple DNA Sequences Alignment Using Heuristic-Based Genetic Algorithm

    Chih-Chin LAI  Shih-Wei CHUNG  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E87-D No:7
      Page(s):
    1910-1916

    The alignment of biological sequences is a crucial tool in molecular biology and genome analysis. A wide variety of approaches has been proposed for multiple sequence alignment problem; however, some of them need prerequisites to help find the best alignment or some of them may suffer from the drawbacks of complexity and memory requirement so they can be only applied to cases with a limited number of sequences. In this paper, we view the multiple sequence alignment problem as an optimization problem and propose a heuristic-based genetic algorithm (GA) approach to solve it. The heuristic/GA hybrid yields better results than other well-known packages do. Experimental results are presented to illustrate the feasibility of the proposed approach.

  • Allocation of Tasks in a DCS Using a Different Approach with A* Considering Load

    Biplab KUMER SARKER  Anil KUMAR TRIPATHI  Deo PRAKASH VIDYARTHI  Laurence T. YANG  Kuniaki UEHARA  

     
    PAPER-Distributed, Grid and P2P Computing

      Vol:
    E87-D No:7
      Page(s):
    1859-1866

    In a Distributed Computing Systems (DCS) tasks submitted to it, are usually partitioned into different modules and these modules may be allocated to different processing nodes so as to achieve minimum turn around time of the tasks utilizing the maximum resources of the existing system such as CPU speed, memory capacities etc. The problem lies on how to obtain the optimal allocation of these multiple tasks by keeping in mind that no processing node is overloaded due to this allocation. This paper proposes an algorithm A*RS, using well-known A*, which aims to reduce the search space and time for task allocation. It aims at minimization of turn around time of tasks in the way so that processing nodes do not become overloaded due to this allocation. Our experimental results justify the claims with necessary supports by comparing it with the earlier algorithm for multiple tasks allocation.

  • Enhancing ICP with P2P Technology: Cost, Availability, and Reconfiguration

    Ping-Jer YEH  Yu-Chen CHUANG  Shyan-Ming YUAN  

     
    PAPER-Networking and System Architectures

      Vol:
    E87-D No:7
      Page(s):
    1641-1648

    Traditional Web cache servers based on HTTP and ICP infrastructure tend to have higher hardware and management cost, have difficulty in availability, automatic and dynamic reconfiguration, and may have slow links to some users. We find that peer-to-peer technology can help solve these problems. The peer cache service (PCS) we proposed here leverages each peer's local cache, similar access patterns, fully distributed coordination, and fast communication channels to enhance response time, scale of cacheable objects, and availability. Moreover, incorporating goals and strategies such as making the protocol lightweight and mutually compatible with existing cache infrastructure, supporting mobile devices, undertaking dynamic three-level caching, and exchanging cache meta-information further improve the effectiveness and differentiate our work from other similar-at-first-glance P2P Web cache systems.

  • Evaluation of the Feedback Guided Dynamic Loop Scheduling (FGDLS) Algorithms

    Sabin TABIRCA  Tatiana TABIRCA  Laurence T. YANG  Len FREEMAN  

     
    PAPER-Distributed, Grid and P2P Computing

      Vol:
    E87-D No:7
      Page(s):
    1829-1833

    In this paper we consider the Feedback-Guided Dynamic Loop Scheduling (FGDLS) method that was proposed by Bull. The method uses a feedback-guided mechanism to schedule a parallel loop within a sequential outer loop. The execution times and the scheduling bounds at a outer iteration are used to find the scheduling bound of the next outer iteration. In this way FGDLS achieves an optimal load balance. Two algorithms have been proposed so far by Tabirca et al. In this article we will review these two algorithms and will give a comparison between their performances.

  • I/O-Efficient Multilevel Graph Partitioning Algorithm for Massive Graph Data

    Jun-Ho HER  R.S. RAMAKRISHNA  

     
    PAPER-Scientific and Engineering Computing with Applications

      Vol:
    E87-D No:7
      Page(s):
    1789-1794

    Graph data in large scientific/engineering applications are often too massive to fit inside the computer's main memory. The resulting input/output (I/O) costs could be a major performance bottleneck. This paper proposes an extension to extant multilevel graph partitioning algorithms with improved I/O-efficiency. The input graph is envisioned as the union of disjoint blocks (subgraphs) of almost the same size. Each block is coarsened in turn. Recursive matching and contraction are the operations in this phase. All the coarsened blocks are then merged in an iterative manner in order to ensure that the resulting graph fits in the main memory. This graph is then treated with an in-core multilevel graph partitioning algorithm in the usual way. Our experimental results show that the larger graph size is, the more dependent on the I/O-efficiency the performance is. And our modification can easily partition very large graphs. It also exhibits considerable improvement in I/O-complexity.

  • Fast Parallel Solution for Set-Packing and Clique Problems by DNA-Based Computing

    Michael (Shan-Hui) HO  Weng-Long CHANG  Minyi GUO  Laurence T. YANG  

     
    PAPER-Scientific and Engineering Computing with Applications

      Vol:
    E87-D No:7
      Page(s):
    1782-1788

    This paper shows how to use sticker to construct solution space of DNA for the library sequences in the set-packing problem and the clique problem. Then, with biological operations, we propose DNA-based algorithms to remove illegal solutions and to find legal solutions for the set-packing and clique problems from the solution space of sticker. Any NP-complete problem in Cook's Theorem can be reduced and solved by the proposed DNA-based computing approach if its size is equal to or less than that of the set-packing problem. Otherwise, Cook's Theorem is incorrect on DNA-based computing and a new DNA algorithm should be developed from the characteristics of the NP-complete problem. Finally, the result to DNA simulation is given.

  • A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters

    Dejiang JIN  Sotirios G. ZIAVRAS  

     
    PAPER-Scientific and Engineering Computing with Applications

      Vol:
    E87-D No:7
      Page(s):
    1774-1781

    The multiplication of large spare matrices is a basic operation in many scientific and engineering applications. There exist some high-performance library routines for this operation. They are often optimized based on the target architecture. For a parallel environment, it is essential to partition the entire operation into well balanced tasks and assign them to individual processing elements. Most of the existing techniques partition the given matrices based on some kind of workload estimation. For irregular sparse matrices on PC clusters, however, the workloads may not be well estimated in advance. Any approach other than run-time dynamic partitioning may degrade performance. In this paper, we apply our super-programming approach to parallel large matrix multiplication on PC clusters. In our approach, tasks are partitioned into super-instructions that are dynamically assigned to member computer nodes. Thus, the load balancing logic is separated from the computing logic; the former is taken over by the runtime environment. Our super-programming approach facilitates ease of program development and targets high efficiency in dynamic load balancing. Workloads can be balanced effectively and the optimization overhead is small. The results prove the viability of our approach.

  • An Acceleration Processor for Data Intensive Scientific Computing

    Cheong Ghil KIM  Hong-Sik KIM  Sungho KANG  Shin Dug KIM  Gunhee HAN  

     
    PAPER-Scientific and Engineering Computing with Applications

      Vol:
    E87-D No:7
      Page(s):
    1766-1773

    Scientific computations for diffusion equations and ANNs (Artificial Neural Networks) are data intensive tasks accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. Thus, this type of tasks naturally maps onto SIMD (Single Instruction Multiple Data stream) parallel processing with distributed memory. This paper proposes a high performance acceleration processor of which architecture is optimized for scientific computing using diffusion equations and ANNs. The proposed architecture includes a customized instruction set and specific hardware resources which consist of a control unit (CU), 16 processing units (PUs), and a non-linear function unit (NFU) on chip. They are effectively connected with dedicated ring and global bus structure. Each PU is equipped with an address modifier (AM) and 16-bit 1.5 k-word local memory (LM). The proposed processor can be easily expanded by multi-chip expansion mode to accommodate to a large scale parallel computation. The prototype chip is implemented with FPGA. The total gate count is about 1 million with 530, 432-bit embedded memory cells and it operates at 15 MHz. The functionality and performance of the proposed processor is verified with simulation of oil reservoir problem using diffusion equations and character recognition application using ANNs. The execution times of two applications are compared with software realizations on 1.7 GHz Pentium IV personal computer. Though the proposed processor architecture and the instruction set are optimized for diffusion equations and ANNs, it provides flexibility to program for many other scientific computation algorithms.

  • Proposal of a Tree Load Balancing Algorithm to Grid Computing Environments

    Rodrigo Fernandes de MELLO  Erico C. T. de MATTOS  Luis Carlos TREVELIN  Maria Stela Veludo de PAIVA  Laurence T. YANG  

     
    PAPER-Software Support and Optimization Techniques

      Vol:
    E87-D No:7
      Page(s):
    1729-1736

    The availability of a low cost hardware has increased the development of distributed systems, by making then more and more accessible. In order to optimize the resources allocation on the distributed systems, some load balancing algorithms have been proposed. These algorithms distribute the application loads over the environment computers, make homogeneous the occupation of the whole environment and increase the application performance. This equal distribution prevents certain computers to get overloaded, to the detriment of the idleness of the other ones. This article proposes and analyzes the TLBAGrid, a load balancing algorithm for Grid computing environments.

  • Traditional File Systems versus DualFS: A Performance Comparison Approach

    Juan PIERNAS  Toni CORTES  Jose M. GARCIA  

     
    PAPER-Software Support and Optimization Techniques

      Vol:
    E87-D No:7
      Page(s):
    1703-1711

    DualFS is a next-generation journaling file system which has the same consistency guaranties as traditional journaling file systems but better performance. This paper introduces three new enhancements which significantly improve DualFS performance during normal operation, and presents different experimental results which compare DualFS and other traditional file systems, namely, Ext2, Ext3, XFS, JFS, and ReiserFS. The experiments carried out prove, for the first time, that a new file system design based on separation of data and metadata can significantly improve file systems' performance without requiring several storage devices.

  • Programming Support for MPMD Parallel Computing in ClusterGOP

    Fan CHAN  Jiannong CAO  Alvin T.S. CHAN  Minyi GUO  

     
    PAPER-Software Support and Optimization Techniques

      Vol:
    E87-D No:7
      Page(s):
    1693-1702

    Many parallel applications involve different independent tasks with their own data. Using the MPMD model, programmers can have a modular view and simplified structure of the parallel programs. Although MPI supports both SPMD and MPMD models for programming, MPI libraries do not provide an efficient way for task communication for the MPMD model. We have developed a programming environment, called ClusterGOP, for building and developing parallel applications. Based on the graph-oriented programming (GOP) model, ClusterGOP provides higher-level abstractions for message-passing parallel programming with the support of software tools for developing and running parallel applications. In this paper, we describe how ClusterGOP supports programming of MPMD parallel applications on top of MPI. We discuss the issues of implementing the MPMD model in ClusterGOP using MPI and evaluate the performance by using example applications.

13161-13180hit(20498hit)