Caching of frequently accessed data has been shown to be a useful technique for reducing congestion on the narrow bandwidth of wireless channels. However, traditional client/server strategies for supporting transactional cache consistency, which require extensive communications between a client and a server, are not appropriate in a wireless mobile database. This paper proposes two, simple but effective, transactional cache consistency protocols for mobile read-only transactions by utilizing the broadcast-based solutions for the problem of invalidating caches. The novelty of our approach is that the consistency check on accessed data and the commitment protocol are implemented in a truly distributed fashion as an integral part of cache invalidation process. The applicability of proposed techniques is also examined by an analytical study.

This paper describes low-power and low-voltage analog circuit techniques applicable to deep sub-micron LSIs in baseband and RF signal processing. The trends indicate that reductions in the supply voltage are inevitable, that power dissipation will not become sufficiently low, and that performance will improve continuously. Some circuit techniques currently being used to achieve these goals are reviewed. Next, three trial approaches are introduced. The first of these is a 1 V operational video-speed CMOS sample-and-hold IC. The second is a 1 V operational high-frequency CMOS VCO circuit. Finally, a step-down DC-DC converter IC with a 1 V output and a greater than 80% power efficiency is introduced. These approaches prove that the low-power and low-voltage operation of analog circuits can be realized without sacrificing performance.

This letter addresses a neural network (NN)-based predictor for the LP (Linear Prediction) residual. A new NN predictor takes into consideration not only prediction error but also quantization effects. To increase robustness against the quantization noise of the nonlinear prediction residual, a constrained back propagation learning algorithm, which satisfies a Kuhn-Tucker inequality condition is proposed. Preliminary results indicate that the prediction gain of the proposed NN predictor was not seriously decreased even when the constrained optimization algorithm was employed.

A quasi-periodic signal is a periodic signal with period and amplitude variations. Several physiological signals, including the electrocardiogram (ECG), can be treated as quasi-periodic. Vector quantization (VQ) is a valuable and universal tool for signal compression. However, compressing quasi-periodic signals using VQ presents several problems. First, a pre-trained codebook has little adaptation to signal variations, resulting in no quality control of reconstructed signals. Secondly, the periodicity of the signal causes data redundancy in the codebook, where many codevectors are highly correlated. These two problems are solved by the proposed codebook replenishment VQ (CRVQ) scheme based on a bar-shaped (BS) codebook structure. In the CRVQ, codevectors can be updated online according to signal variations, and the quality of reconstructed signals can be specified. With the BS codebook structure, the codebook redundancy is reduced significantly and great codebook storage space is saved; moreover variable-dimension (VD) codevectors can be used to minimize the coding bit rate subject to a distortion constraint. The theoretic rationale and implementation scheme of the VD-CRVQ is given. The ECG data from the MIT/BIH arrhythmic database are tested, and the result is substantially better than that of using other VQ compression methods.

The potential network architecture of the emerging carrier class VoIP (Voice over IP) technology for NGN (Next Generation Networks) adopts distributed control architecture to take full advantage of scalability, reliability, flexibility, and interoperability. However, the design of distributed control architecture in the carrier class VoIP network is the state-of-the-art in decentralization and distribution of control. Different configurations of system elements, control scheme of inter system elements communications, signaling protocol, functional partitioning, and scheduling of jobs in call control processing may affect the system performance and QoS (Quality of Service) of MGC (Media Gateway Controller) in carrier class VoIP network. Hence, the modeling of distributed control architecture and its performance analysis are essential issues whenever optimum control architecture has to be determined to meet design requirements. Based on these reasons, this paper proposes several potential network architectures and focuses on the performance study of distributed control architecture in carrier class VoIP network. The SIGTRAN-based distributed control architecture model and the MGCP/MEGACO-based distributed control architecture model are presented. Then, we analyze the SIGTRAN-based distributed control architecture model between MGC and SG (Signaling Gateway) using WRR (Weighted Round Robin) and WF2Q (Worst-case Fair Weighted Fair Queueing) scheduling algorithms respectively. And, we analyze the MGCP/MEGACO-based distributed control architecture model between MGC and MG (Media Gateway) using M/G/1 gating service queueing model. Consequently, the results of performance analysis can be used to evaluate whether the performance of distributed control architecture model can meet the requirement of planning and design for carrier class VoIP network deployment.

In this paper, we propose a novel higher order time-frequency distribution (GDH) for a discrete time signal. This distribution is defined over the original discrete time-frequency grids through a delicate discretization of an equivalent expression of a higher order distribution, for a continuous time signal, in [4]. We also present a constructive design method, for the kernel of the GDH, by which the distribution satisfies (i) the alias free condition as well as (ii) the marginal conditions. Numerical examples show that the proposed distributions reasonably suppress the artifacts which are observed severely in the Wigner distribution and its simple higher order generalization.

A digital calibration technique, which corrects errors due to capacitor mismatch in pipelined ADC and directly measures the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.5 dB, a peak integral non-linearity of 0.3 LSB, and a peak differential non-linearity of 0.3 LSB using the digital calibration.

The Fat-Btree which is a new parallel B-tree structure has been proposed to improve the access performance of shared-nothing parallel database systems. Since the Fat-Btree has only a part of index nodes on each processing element, it can reduce the synchronization cost in update operations. For these reasons, both retrieval and update operations can be processed at high throughput compared to previously proposed parallel B-tree structures for shared-nothing computers. Though we tried to apply some conventional concurrency control methods to the Fat-Btree, e.g., B-OPT and ARIES/IM, which were designed for shared-everything machines, we found that these methods are not always appropriate for the Fat-Btree. In this paper, it is shown that the conventional methods are not suitable for the Fat-Btree and other parallel B-trees. We propose a new deadlock free concurrency control protocol, named INC-OPT, to improve the performance of the Fat-Btree more effectively than the B-OPT and ARIES/IM. Furthermore, in order to prove that the Fat-Btree provides the impact on the performance of shared-nothing parallel databases, we compare the real performance of three types of parallel B-tree structures, Fat-Btree, Copy-Whole-Btree, and Single-Index-Btree, on an nCUBE3 machine where the INC-OPT is applied.

In this paper, we investigate the optimal assignment problem of cells in PCS (Personal Communication Service) to switches on a ATM (Asynchronous Transfer Mode) network. Given cells and switches on an ATM network (whose locations are fixed and known), the problem is to group cells into clusters and assign these clusters to switches in an optimum manner. This problem is modeled as a complex integer programming problem. Since finding an optimal solution of this problem is NP-hard, a heuristic solution model consists of three phases (Cell Pre-Partitioning Phase, Cell Exchanging Phase, and Cell Migrating Phase) is proposed. Experimental results show that Cell Exchanging and Cell Migrating Phases can really reduce total cost near 44% on average.

Lossless video coding is required in the fields of archiving and editing digital cinema or digital broadcasting contents. This paper proposes multiresolution lossless video coding using a discrete wavelet transform and adaptive inter/intra-frame prediction in the wavelet domain. The multiresolution structure based on the wavelet transform facilitates interchange among several video source formats such as Super High Definition (SHD) images, HDTV, SDTV, and mobile applications. In order to increase the compression ratio, and to keep the computational cost low, the adaptive inter/intra-frame prediction is performed in the lowest wavelet transform domain. The adaptive inter/intra-frame prediction can adapt to changes in the local inter/intra-frame statistics. Experiments on digital cinema test sequences confirm effectiveness of the proposed algorithm.

This paper presents the performance modeling, analysis, and simulation of SIP-T (Session Initiation Protocol for Telephones) signaling system in carrier class packet telephony network for NGN (Next Generation Networks). Until recently, fone of the greatest challenges in the migration from existing PSTN (Public Switched Telephone Network) toward NGN is to build a carrier class packet telephony network that preserves the ubiquity, quality, and reliability of PSTN services while allowing the greatest flexibility for use of new packet telephony technology. The SIP-T signaling system defined in IETF (Internet Engineering Task Force) draft is a mechanism that uses SIP (Session Initiation Protocol) to facilitate the interconnection of PSTN with carrier class packet telephony network. Based on IETF, the SIP-T signaling system not only promises scalability, flexibility, and interoperability with PSTN but also provides call control function of MGC (Media Gateway Controller) to set up, tear down, and manage VoIP (Voice over IP) calls in carrier class packet telephony network. In this paper, we derive the buffer size, the mean of queueing delay, and the variance of queueing delay of SIP-T signaling system that are the major performance evaluation parameters for improving QoS (Quality of Service) and system performance of MGC in carrier class packet telephony network focused on toll by-pass or tandem by-pass of PSTN. First, we assume a mathematical model of the M/G/1 queue with non-preemptive priority assignment to represent SIP-T signaling system. Second, we derive the formulas of buffer size, queueing delay, and delay variation for the non-preemptive priority queue by queueing theory respectively. Besides, some numerical examples of buffer size, queueing delay, and delay variation are presented as well. Finally, the theoretical estimates are shown to be in excellent consistence with simulation results.

In SoC (system-on-a-chip) design, interfacing among IP (Intellectual Property) blocks is one of the most important issues. Since most IP's are provided by different vendors, they generally have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method with two features: 1) generation of the interface between IP's with different operating frequencies, and 2) minimization of the hardware resource required for the interface. We have demonstrated the proposed algorithm through its application to an MP3 decoder design example, where the IIS (Inter-IC Sound)-to-PCI (Peripheral Component Interconnect) protocol converter was successfully implemented using the proposed method.

Pilot-aided adaptive prediction channel estimation is proposed for coherent detection in a frequency-nonselective fading channel. It is an extension of the conventional weighted multi-slot averaging (WMSA) channel estimation and consists of 3 steps. A block of Np pilot symbols is periodically transmitted, each pilot block being followed by Nd data symbols to form a data slot. In the first step, the instantaneous channel gain is estimated by coherent addition of Np pilot symbols. Using the K past and K future estimated instantaneous channel gains, the second step predicts the instantaneous channel gains at the end and beginning of data slot of interest by a forward predictor and a backward predictor, respectively. The tap-weights of forward prediction and backward prediction are adaptively updated using the normalized least mean square (NLMS) algorithm. Finally, in the third step, the instantaneous channel gain at each data symbol position within the data slot of interest is estimated by simple averaging or linear interpolation using the two adaptively predicted instantaneous channel gains. The computer simulation confirms that the proposed adaptive prediction channel estimation achieves better bit error rate (BER) performance than the conventional WMSA channel estimation in a fast fading channel and/or in the presence of frequency offset between a transmitter and a receiver.

A voltage-mode universal biquadratic filter using single current-feedback amplifier (CFA), two capacitors and three resistors is presented. The new circuit has four inputs and one output and can realize all the standard filter functions, that is, lowpass, bandpass, highpass, notch and allpass filters, without changing the circuit topology. The use of only one current-feedback amplifier simplifiers the configuration.

Hypercomplex coefficient digital filters provide several attractive advantages such as compact realization with reduced system order, inherent parallelism. However, they also possess a drawback in that a multiplier requires a large amount of computations. This paper proposes a computationally efficient implementation of digital filters whose coefficient is a type of hypercomplex number; a bicomplex number. By decomposing a bicomplex multiplier into two parallel complex multipliers, we show that hypercomplex digital filters can be implemented as two parallel complex digital filters. The proposed implementation offers more than a 60% reduction in the count of real multipliers.

The effect of subarray size (equal to the order of the prediction model plus one) on the estimation performance of a previously proposed forward-backward linear prediction (FBLP) based cyclic method is investigated. This method incorporates an overdetermined FBLP model with a subarray scheme and is used to estimate the directions-of-arrival (DOAs) of coherent cyclostationary signals impinging on a uniform linear array (ULA) from the corresponding polynomial or spectrum formed by the prediction coefficients. However, the decorrelation is obtained at the expense of a reduced working array aperture, as it is with the spatial smoothing (SS) technique. In this paper, an analytical expression of the mean-squared-error (MSE) of the spectral peak position is derived using the linear approximation for higher signal-to-noise ratio (SNR). Then the subarray size that minimizes this approximate MSE is identified. The effect of subarray size on the DOA estimation is demonstrated and the theoretical analysis is substantiated through numerical examples.

Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4 µs and a total settling time of 10 µs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142 ps and a power consumption of 470 µW.

In this paper, we show that a priori probabilities of information bits can be incorporated into metrics for syndrome decoding. Then it is confirmed that soft-in/soft-out decoding is also possible for syndrome decoding in the same way as for Viterbi decoding. The derived results again show that the two decoding algorithms are dual to each other.

In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm 800 µm and it dissipates about 210 mW at 3 V power supply. The INL is within 1 LSB and DNL is within 1 LSB, respectively. The SNR is about 43 dB, when the input frequency is 10 MHz at 200 MHz clock frequency.

Adaptive optimization of the notch bandwidth of a lattice-based adaptive infinite impulse response (IIR) notch filter is presented in this paper. The filter is used to improve the performance of a direct sequence spread spectrum (DSSS) binary phase shift keying (BPSK) communication system by suppressing a narrow-band interference at the receiver. A least mean square (LMS) algorithm used to adapt the notch bandwidth coefficient to its optimum value which corresponds to the maximum signal to noise ratio (SNR) improvement factor is derived. Bit error rate (BER) improvement gained by the DSSS communication system using the filter with the optimized notch bandwidth is also shown. Computer simulation results are compared with those obtained analytically to demonstrate the validity of theoretical predictions for various received signal parameters.