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14481-14500hit(20498hit)

  • A Time-Domain Joint Adaptive Channel Estimator and Equalizer for Multi-Carrier Systems in Time-Variant Multipath Channels Using Short Training Sequences

    Wichai PONGWILAI  Sawasd TANTARATANA  

     
    PAPER-Wireless Communication Technology

      Vol:
    E85-B No:12
      Page(s):
    2797-2806

    In this paper, a new approach is proposed to improve the channel estimation accuracy with channel tracking capability for adaptive multicarrier equalization systems under time-variant multipath fading channel. The improvement is carried out based on the assumption that the channel is static over a transmitted block period, and slowly linearly changing over several block periods. By applying IFFT to the concatenated channel transfer function derived from different blocks, the noise-averaging improvement is achieved, and a better estimation of the channel coefficients with some delay can be obtained. A multi-step channel predictor and a smoothing filter is utilized to compensate for the delay and make the system more robust in terms of channel tracking performance. Adaptive time domain equalization is jointly performed with this approach to avoid the channel invertibility problem found in the frequency domain approach. A short period of training sequences is utilized resulting in more efficient use of available communication capacity. The effectiveness of the proposed approach is evaluated through simulation for multicarrier systems in time-variant multipath fading channels. Results show improvement over previous channel estimation schemes.

  • Cost-Effective Analysis of Software Systems with Periodic Rejuvenation

    Hiroaki SUZUKI  Tadashi DOHI  Hiroyuki OKAMURA  

     
    PAPER-Reliability, Maintainability and Safety Analysis

      Vol:
    E85-A No:12
      Page(s):
    2923-2932

    In this paper, we consider the similar software cost models with periodic rejuvenation to Garg, Puliafito, Telek and Trivedi (1995) under the cost effectiveness criteria. First, an alternative model as well as the original one are analyzed by Markov regenerative processes. We derive analytically the optimal periodic software rejuvenation policies which maximize the cost-effectiveness in the steady state for two models. Further, we develop statistical non-parametric algorithms to estimate the optimal software rejuvenation policies, provided that the sample data to characterize the system failure times are given. Then, the total time on test (TTT) concept is used. In numerical examples, we compare the periodic software rejuvenation policy with the non-periodic one, and investigate the asymptotic properties of the non-parametric estimators for the optimal software rejuvenation policies through a simulation experiment.

  • Design Exploration of an Industrial Embedded Microcontroller: Performance, Cost and Software Compatibility

    Ing-Jer HUANG  Li-Rong WANG  Yu-Min WANG  Tai-An LU  

     
    PAPER-VLSI Design

      Vol:
    E85-A No:12
      Page(s):
    2624-2635

    This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

  • A High Performance Fault-Tolerant Dual-LAN with the Dual-Path Ethernet Module

    Jihoon PARK  Jongkyu PARK  Ilseok HAN  Hagbae KIM  

     
    PAPER-Network

      Vol:
    E85-B No:12
      Page(s):
    2880-2886

    The network duplicating can achieve significant improvements of the Local Area Network (LAN)'s performance, availability, and security. For LAN duplicating, a Dual-Path Ethernet Module (DPEM) is developed. Since a DPEM is simply located at the front end of any network device as a transparent add-on type independent hardware machine, it does not require sophisticated server reconfiguration. We examine the desirable properties and the characteristics on the Dual-LAN structure. Our evaluation results show that the developed scheme is more efficient than the conventional Single-LAN structures in various aspects.

  • Optical Switching Phenomena of Kerr Nonlinear Microsphere Due to Near-Field Coupling: Numerical Analysis

    Masanobu HARAGUCHI  Toshihiro OKAMOTO  Masuo FUKUI  

     
    PAPER

      Vol:
    E85-C No:12
      Page(s):
    2059-2064

    We calculated linear and nonlinear responses of a Kerr nonlinear microsphere sandwiched by two prisms using the excitation of whispering gallery modes due to near-field coupling. As numerical calculations, the finite-difference time-domain method that takes into account the Kerr nonlinear effect was used. We dealt with two types of spheres, i.e., the Kerr-material sphere and the dielectric sphere coated by the Kerr material. It was found that the optical switching phenomena are induced in such spheres. The switching results from the fact that the variations of the refractive index of the nonlinear spheres affect the excitation condition of the whispering gallery modes.

  • Multiple Delay Bounds Control Algorithm via Class-Level Service Curves

    Daein JEONG  H. Jonathan CHAO  Hwasung KIM  

     
    PAPER-Network

      Vol:
    E85-B No:12
      Page(s):
    2868-2879

    In this paper, we propose a packet-scheduling algorithm, called the Class-level Service Lagging (CSL) algorithm, that guarantees multiple delay bounds for multi-class traffic in packet networks. We derive the associated schedulability test conditions, which are used to determine call admission. We first introduce a novel implementation of priority control, which has a conventional and simple form. We show how the efforts to confirm the logical validity of that implementation are managed to reach the definition of the CSL algorithm. The priority control is realized by imposing class-level unfairness in service provisioning, while the underlying service mechanism is carried out using the notion of fair queueing. The adoption of fair queueing allows the capability to maintain the service quality of the well-behaving traffic even in the presence of misbehaving traffic. We call this the firewall property. Simulation results demonstrate the superiority of the CSL algorithm in both priority control and firewall functionality. We also describe how the CSL algorithm is implementable with a computational complexity of O(1). Those features as well as the enhanced scalability, which results from the class-level approach, confirm the adequacy of the CSL algorithm for the fast packet networks.

  • Heuristic and Exact Algorithms for QoS Routing with Multiple Constraints

    Gang FENG  Kia MAKKI  Niki PISSINOU  Christos DOULIGERIS  

     
    PAPER-Network

      Vol:
    E85-B No:12
      Page(s):
    2838-2850

    The modern network service of finding the optimal path subject to multiple constraints on performance metrics such as delay, jitter, loss probability, etc. gives rise to the multi-constrained optimal-path (MCOP) QoS routing problem, which is NP-complete. In this paper, this problem is solved through both exact and heuristic algorithms. We propose an exact algorithm E_MCOP, which first constructs an aggregate weight and then uses a K-shortest-path algorithm to find the optimal solution. By means of E_MCOP, the performance of the heuristic algorithm H_MCOP proposed by Korkmaz et al. in a recent work is evaluated. H_MCOP only runs Dijkstra's algorithm (with slight modifications) twice, but it can find feasible paths with a success ratio very close to that of the exact algorithm. However, we notice that in certain cases its feasible solution has an unsatisfactorily high average cost deviation from the corresponding optimal solution. For this reason, we propose some modified algorithms based on H_MCOP that can significantly improve the performance by running Dijkstra's algorithm a few more times. The performance of the exact algorithm and heuristics is investigated through computer simulations on networks of various sizes.

  • Data Transfer Time by HTTP 1.0/1.1 on Asymmetric Networks Composed of Satellite and Terrestrial Links

    Hiroyasu OBATA  Kenji ISHIDA  Junichi FUNASAKA  Kitsutaro AMANO  

     
    PAPER-Internet

      Vol:
    E85-B No:12
      Page(s):
    2895-2903

    Asymmetric networks, which provide asymmetric bandwidth or delay for upstream and downstream transfer, have recently gained much attention since they support popular applications such as the World Wide Web (WWW). HTTP (Hypertext Transfer Protocol) is the basis of most WWW services so, evaluating the performance of HTTP on asymmetric networks is increasingly important, particularly real-world networks. However, the performance of HTTP on the asymmetric networks composed of satellite and terrestrial links has not sufficiently evaluated. This paper proposes new formulas to evaluate the performance of both HTTP1.0 and HTTP1.1 on asymmetric networks. Using these formulas, we calculate the time taken to transfer web data by HTTP1.0/1.1. The calculation results are compared to the results of an existing theoretical formula and experimental results gained from a system that combines a VSAT (Very Small Aperture Terminal) satellite communication system for satellite links (downstream) and the Internet for terrestrial links (upstream). The comparison shows that the proposed formulas yield more accurate results (compared to the measured values) than the existing formula. Furthermore, this paper proposes an evaluation formula for pipelined HTTP1.1, and shows that the values output by the proposed formula agree with those obtained by experiments (on the VSAT system) and simulations.

  • An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs

    Yusuke MATSUNAGA  

     
    PAPER-Logic Synthesis

      Vol:
    E85-A No:12
      Page(s):
    2715-2724

    Functional decomposition is an essential technique of logic synthesis and is important especially for FPGA design. Bertacco and Damiani proposed an efficient algorithm finding simple disjoint decomposition using Binary Decision Diagrams (BDDs). However, their algorithm is not complete and does not find all the decompositions. This paper presents a complete theory of simple disjoint decomposition and describes an efficient algorithm using BDDs.

  • SP2: A Very Large-Scale Event Driven Logic Simulation Hardware

    Hirofumi HAMAMURA  Hiroaki KOMATSU  

     
    PAPER-Logic Simulation

      Vol:
    E85-A No:12
      Page(s):
    2737-2745

    This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

  • A Performance-Driven Floorplanning Method with Interconnect Performance Estimation

    Shinya YAMASAKI  Shingo NAKAYA  Shin'ichi WAKABAYASHI  Tetsushi KOIDE  

     
    PAPER-Physical Design

      Vol:
    E85-A No:12
      Page(s):
    2775-2784

    In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

  • Design of Asynchronous Controllers with Delay Insensitive Interface

    Hiroshi SAITO  Alex KONDRATYEV  Jordi CORTADELLA  Luciano LAVAGNO  Alex YAKOVLEV  Takashi NANYA  

     
    PAPER-Design Methodology

      Vol:
    E85-A No:12
      Page(s):
    2577-2585

    Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

  • Quality-Driven Design for Video Applications

    Yun CAO  Hiroto YASUURA  

     
    PAPER-Design Methodology

      Vol:
    E85-A No:12
      Page(s):
    2568-2576

    This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

  • Increase in Delay Uncertainty by Performance Optimization

    Masanori HASHIMOTO  Hidetoshi ONODERA  

     
    LETTER-Timing Analysis

      Vol:
    E85-A No:12
      Page(s):
    2799-2802

    This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay times of long paths are shortened and the delay times of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which is caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of circuit delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

  • Accelerating Logic Rewiring Using Implication Analysis Tree

    Chin-Ngai SZE  Wangning LONG  Yu-Liang WU  Jinian BIAN  

     
    PAPER-Logic Synthesis

      Vol:
    E85-A No:12
      Page(s):
    2725-2736

    In this paper, we present a novel algorithm to the alternative wiring problem by analyzing the implication relationship between nodes of alternative wires. Alternative wiring, or rewiring, refers to the process of adding a redundant connection to a circuit so as to make a target connection redundant and removable from the circuit without altering the functionality of the circuit. The well-known ATPG-based alternative wiring scheme, Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. But, the deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires. Our approaches of redundancy identification by source node and destination node implication relationship indicate that a large subset of unnecessary redundancy check processes can be further avoided to improve the efficiency significantly. We propose an algorithm, the Implication Based Alternative Wiring Logic Transformation (IBAW), to integrate the two adroit techniques. IBAW provides a competent solution to the alternative wiring problem and shows an outstanding efficiency in our experiments. Experiments were performed on MCNC benchmark circuits. Results show that IBAW runs 6.8 times faster than the original RAMBO in locating alternative wires and solution quality is maintained.

  • An Optimal File Transfer on Networks with Plural Original Files

    Yoshihiro KANEKO  Shoji SHINODA  

     
    PAPER-Graphs and Networks

      Vol:
    E85-A No:12
      Page(s):
    2913-2922

    A problem of obtaining an optimal file transfer of a file transmission net N is to consider how to transmit, with the minimum total cost, copies of a certain file of information from some vertices, called sources, to other vertices of N by the respective vertices' copy demand numbers. This problem is NP-hard for a general file transmission net N. Some classes of N, on each of which a polynomial time algorithm for obtaining an optimal file transfer can be designed, are known. In the characterization, we assumed that file given originally to the source remains at the source without being transmitted. In this paper, we relax the assumption to the one that a sufficient number of copies of the file are given to the source and those copies can be transmitted from the source to other vertices on N. Under this new assumption, we characterize a class of file transmission nets, on each of which a polynomial time algorithm for obtaining an optimal file transfer can be designed. A minimum spanning tree with degree constraints plays a key role in the algorithm.

  • Analysis of Multicasting Strategies for VP-Based ATM Networks

    Bih-Hwang LEE  Shih-Fan SHIE  

     
    PAPER-Network

      Vol:
    E85-B No:12
      Page(s):
    2851-2858

    In ATM networks, call processing on switches can be greatly simplified by using the concept of virtual path (VP); and good resource management strategies ensure that virtual channel connections (VCC) can be rapidly and efficiently established. In order to have good system performance, several methods of constructing virtual paths and strategies of allocating and managing resources should be considered. In this paper, several multicast strategies with dynamic routing are used and applied to the metropolitan LATA network. For the VP-based network, dynamic routing is also applied, and those strategies are discussed and investigated to show the versatility of the approach. Some results using dynamic multicast routing, such as call blocking rate, VP utilization, and VP adjustment rate, are obtained for the different strategies by simulation experiments.

  • Fluorescence Spectroscopy of Rb Atoms with Two-Color Optical Near Fields for a High-Resolution Slit-Type Detector

    Kouki TOTSUKA  Haruhiko ITO  Motoichi OHTSU  

     
    PAPER

      Vol:
    E85-C No:12
      Page(s):
    2093-2096

    We introduce stepwise resonant excitation by two-color optical near fields in order to detect Rb atoms with a slit-type detector. Blue fluorescence of the second D2 line is monitored for background-free detection. Feasibility of the method is shown from an experiment with a Rb vapor cell, where a sub-Doppler spectrum with the FWHM of 80 MHz is obtained. The detection efficiency is estimated at about 3% for cold Rb atoms.

  • A Super-Resolution Time Delay Estimation Based on the MUSIC-Type Algorithm

    Feng-Xiang GE  Qun WAN  Jian YANG  Ying-Ning PENG  

     
    PAPER-Antenna and Propagation

      Vol:
    E85-B No:12
      Page(s):
    2916-2923

    The problem of the super-resolution time delay estimation of the real stationary signals is addressed in this paper. The time delay estimation is first converted into a frequency estimation problem. Then a MUSIC-type algorithm to estimate the subsequent frequency from the single-experiment data is proposed, which not only avoids the mathematical model mismatching but also utilizes the advantages of the subspace-based methods. The mean square errors (MSEs) of the time delay estimate of the MUSIC-type method for varying signal-to-noise (SNR) and separation of two received signal components are shown to illustrate that they approximately coincide with the corresponding Cramer-Rao bound (CRB). Finally, the comparison between the MUSIC-type method and the other conventional methods is presented to show the advantages of the proposed method in this paper.

  • A New OFDM Demodulation Method with Variable-Length Effective Symbol and ICI Canceller

    Noriyoshi SUZUKI  Hideyuki UEHARA  Mitsuo YOKOYAMA  

     
    PAPER

      Vol:
    E85-A No:12
      Page(s):
    2859-2867

    In an orthogonal frequency division multiplexing (OFDM) system, the bit error performance is degraded in the presence of multiple propagation paths whose excess delays are longer than the Guard Interval (GI), because the orthogonality between subcarriers cannot be maintained. In this paper, we propose a new OFDM demodulation method with a variable-length effective symbol and a multi-stage inter-carrier interference (ICI) canceller, in order to improve the bit error performance in the presence of multipaths whose excess delays are longer than the GI. The influence of the inter-symbol interference (ISI) is eliminated by the variable-length effective symbol, and then the ICI component is reduced by the multi-stage ICI canceller. The principle of the proposed method is explained, and the performance of the proposed method is then evaluated by computer simulation. The results show that the proposed method improves the system availability under more various multipath fading environments without changing the system parameters.

14481-14500hit(20498hit)