In this paper, an infinite-horizon team-optimal incentive Stackelberg strategy is investigated for a class of stochastic linear systems with many non-cooperative leaders and one follower. An incentive structure is adopted which allows for the leader's team-optimal Nash solution. It is shown that the incentive strategy set can be obtained by solving the cross-coupled stochastic algebraic Riccati equations (CCSAREs). In order to demonstrate the effectiveness of the proposed strategy, a numerical example is solved.

Two voltage controlled current source (VCCS) models of double-channel p-type lateral extended drain MOS (DPLEDMOS) are firstly proposed to analyze the energy recovery circuit (ERC) efficiency of PDP data driver IC. In terms of the mathematical function between ID and VDS, the VCCS models are created. The presented models can be embedded in system software Saber to simulate the ERC waveform of data driver IC. A test board and a PDP system are used to verify the accuracy of the VCCS models. The experimental measurements agree with the simulation results very well and the maximum model error is 3.89%. Simulation results also show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time TERC, the drain current ID, and the capacitance of CL. In an actual PDP system, TERC is restricted and CL is changeless. The ERC efficiency of PDP data driver IC can be improved significantly by using DPLEDMOS which has higher ID capacity. The proposed VCCS models of DPLEDMOS can be used to predict the ERC efficiency accurately.

This letter is concerned with cellular controlled short-range communication (CCSRC) systems, which can provide a significant performance gain over the traditional cellular systems as shown in the literature. However, to obtain such a gain, CCSRC systems need perfect channel state information (CSI) of all users and the complexity of setting up the optimal cooperative clusters is factorial with respect to the number of potentially cooperative users, which is very unrealistic in practical systems. To solve this problem, we propose a novel cooperative strategy, where CCSRC systems only need the distances between all user pairs and the complexity of setting up the cooperative clusters is relatively low. Simulation results show that the performance of the proposed strategy is close to optimal.

The bit-error-rate (BER) performance predicted by the semi-analytical evolution technique proposed by Li Ping et al. becomes inaccurate for parallel concatenated coded interleave-division multiple-access (PCC-IDMA) systems. To solve this problem, we develop a novel evolution technique of such systems. Numerical results show that the predicted performance agrees well with the simulation results, and that this technique is useful for system optimization.

We propose a shot reduction technique of character projection (CP) Electron Beam Direct Writing (EBDW) using combined cell stencil (CCS) or the advanced process technology. CP EBDW is expected both to reduce mask costs and to realize quick turn around time. One of major issue of the conventional CP EBDW, however, is a throughput of lithography. The throughput is determined by numbers of shots, which are proportional to numbers of cell instances in LSIs. The conventional shot reduction techniques focus on optimization of cell stencil extraction, without any modifications on designed LSI mask patterns. The proposed technique employs the proposed combined cell stencil, with proposed modified design flow, for further shot reduction. We demonstrate 22.4% shot reduction within 4.3% area increase for a microprocessor and 28.6% shot reduction for IWLS benchmarks compared with the conventional technique.

This letter introduces a chaotic circuit consisting of one linear 2-port VCCS, one hysteresis 2-port VCCS, and two capacitors. The circuit has double screw attractors, quad screw attractors and co-existence states of them. Since the system is piecewise linear, attractors existence condition can be described using exact piecewise solutions. Using a simple test circuit, typical phenomena are verified in the laboratory.

Fairness is one of the important notion for programming language, such as process algebras like CCS, that includes concurrency (or parallelism) and nondeterminism. This ensures that while repeatedly choosing among a set of alternatives, no alternative will be postponed forever. However, the fairness does not mention at what frequency these alternatives are selected. In this paper, we propose a quantitative fairness, which is called economic-oriented fairness, to each alternatives. This fairness ensures that the expected number of selection for each alternatives are same. We give a condition for probability assignment of selection of each alternative to be satisfied for economic-oriented fairness. First we show a simple probability assignment rule. In this assignment, between any two alternatives, if an alternative is selected n times and the other m times then the probability to select the former alternative is (m + 1)/(n + 1) times the probability for the latter. We prove that this assignment satisfies the condition of economic-oriented fairness. For a model of the economic-oriented fairness, we adopt a probabilistic process algebra. Finally, we elaborate with two process models of the economic-oriented fairness. The first one is a server and client model, where each client communicates only with the server, but not among them. In this model, the expected number of communication by each client are equal. The second model considers communication between two processes. In practice, a process has several subprocesses. Each subprocess communicates via a communication port, In the second model, there is economic-oriented fairness where the expected number of communications via each communication port are equal.

This paper considers algebraic basic processes, a subset of communicating processes in CCS by Milner, and presents a synthesis algorithm to infer a process that satisfies the properties of the process, represented as fomulae in Hennessy-Milner Logic. The validity of the proposed algorithm can be stated that it synthesizes a process in the limit, which cannot be distinguished from the target one with respect to the strong equivalence.

This paper presents an effective application of Net-theory for all the stages of the communication protocol development process. Net-theory provides a basic mathematical model and tool for development of communication protocol. The special usability of Net-theory is that 1) visual representation of the system's stadic/dynamic structure, so that users may easily understand the represented contents, 2) formal specifications based on mathematical basis of Net-theory admit automatic verification, implementation and conformance testing. We have seen that Net-theory which has the above usability can provide a systematic and advanced paradigm for effective communication protocol development.

We often use data flow diagrams or state transition diagrams to design software systems with concurrency. We call those diagrams as nets in this paper. Semantics of any methods to describe such software systems should be defined in some formal ways. There would be no doubts that any nets should be supported by appropriate theoretical frameworks. In this paper, we use CCS as a typical algebraic approach of using formulas to express concurrent behaviors and point out the different features of CCS from Petri nets. Any approaches should be not only theoretically beautiful but also practically useful. We use a specification language LOTOS as such example which has two features, CCS and ADT, and is designed to specify practical communication protocols. Algebraic approaches of using formulas, like LOTOS, can be considered as a compact way to express concurrent behaviors. We explore our discussions of net-oriented approaches into UIMS research fields. After mentioning state transition models of UIMS, we exemplify a practically used example, VIA-UIMS, which has been developed by one of authors. VIA-UIMS employs a net-oriented architecture. It has been designed to reconstuct tools which have already been widely used in many sites.

The Consultative Committee of Space Data Systems (CCSDS) proposes a packetized telemetry scheme for the convenience of data exchange and networking in space activity. This paper describes the outline of the telemetry scheme and the on-orbit experiment which was carried out to show the applicability of the proposed CCSDS packet telemetry scheme using the Japan's satellite "Hiten" in a highly elliptical orbit. The telemetry data which are generated by the onboard instruments are packetized in Hiten, and reformed to the original data in earth stations successfully. The experimental results show that the standardized scheme is helpful for tracking cross-support between organizations, and that the concatenated code is quite effective to transmit data in a low C/N condition.

Up to present, some automatically tunable active RC filters have been proposed for the monolithic integrated continuous-time filters. In this paper a synthesis method of monolithic active RC filters is presented, whose characteristic is hardly dependent on temperature, supply voltage and so on, theoretically. First, this paper describes a variable integrator controlled by bias current. Second, a resistor controlled current source circuit (RCCS) is also proposed, which contains the voltage controlled current source (VCCS) being identical with that used in the realization of the integrator and whose current is controlled by an external resistor. The use of this VCCS in the RCCS can completely compensate the variation of the integrator characteristics. Finally, these circuits are applied to realize a third-order elliptic low-pass filter, which is simulated on PSPICE. From the simulations, we obtain excellent results as follows: The deviation of gains in the passband due to the variation of temperature with a range of -10 to 60 is within 0.02 dB; A total harmonic distortion with a 1 Vp-p input voltage at 100 kHz is less than 0.4% when the cut-off frequency is 1 MHz and the supply voltage is 5 V.