In this paper, a novel trench MOS barrier Schottky contact super barrier rectifier (TMB-SSBR) is proposed by combining the advantages of vertical SSBR and conventional TMBS. The operation mechanism and simulation verification are presented. TMB-SSBR consists of MOS trenches with a vertical SSBR grid which replaces the Schottky diode in the mesa of a TMBS. Due to the presence of top p-n junction in the proposed TMB-SSBR, the image force barrier lowering effect is eliminated, the pinching off electric field effect by MOS trenches is weakened, so that the mesa surface electric field is much larger than that in conventional TMBS. Therefore, the mesa width is enlarged and the n-drift concentration is slightly increased, which results in a low specific on-resistance and a good tradeoff between reverse leakage currents and forward voltages. Compared to a conventional TMBS, simulation results show that, with the same breakdown voltage of 124V and the same reverse leakage current at room temperature, TMB-SSBR increases the figure of merit (FOM, equates to VB2/Ron, sp) by 25.5%, and decreases the reverse leakage by 33.3% at the temperature of 423K. Just like the development from SBD to TMBS, from TMBS to TMB-SSBR also brings obvious improvement of performance.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

In this paper, a new non-uniform weight-updating scheme for adaptive digital beamforming (DBF) is proposed. The unique feature of the letter is that the effective working range of the beamformer is extended and the computational complexity is reduced by introducing the robust DBF based on worst-case performance optimization. The robust parameter for each weight updating is chosen by analyzing the changing rate of the Direction of Arrival (DOA) of desired signal in LEO satellite communication. Simulation results demonstrate the improved performance of the new Non-Uniform Weight-Updating Beamformer (NUWUB).

The information maximization (Infomax) based on information entropy theory is a class of methods that can be used to blindly separate the sources. Torkkola applied the Infomax criterion to blindly separate the mixtures where the sources have been delayed with respect to each other. Compared to the frequency domain methods, this time domain method has simple adaptation rules and can be easily implemented. However, Torkkola's method works only in the real valued field. In this letter, the Infomax for blind separation of the delayed sources is extended to the complex case for processing of complex valued signals. Firstly, based on the gradient ascent the adaptation rules for the parameters of the unmixing network are derived and the steps of algorithm are given. Then, a measurement matrix is constructed to evaluate the separation performance. The results of computer experiment support the extended algorithm.

This article discusses on PDM (Petri net based Development Methodology) which integrates approaches, modeling methods, design methods and analysis methods in a coherent manner. Although various development techniques based on Petri nets have demonstrated advantages over conventional techniques, those techniques are rather ad hoc and lack an overall picture on entire development process. PDM anticipates to provide a refernce process model to develop distributed systems with various Petri net based development methods. Behavioral properties of distrbuted systems can be an appropriate application domain of PDM.

A new class of (m23m1,m2) 1-step majority-logic decodable double error correcting codes (1-step DEC codes) is described, where m is an odd integer. Combining this code with properly constructed (m1k1,k1) and (m,k2) 1-step DEC codes, a (m23(mk1)1,m23k1) 1-step DEC code and a (m23(mk2)1,m2) 2-step majority-logic decodable DEC code (2-step DEC code) are obtained, respectively. Considering computer memory applications, some practical 1 -and 2-step DEC codes with data-bit lengths of 24, 32, 64 and 72 are obtained by shortening the new codes, and are compared to existing majority-logic decodable DEC codes. It is shown that, for given data-bit lengths, new 2-step DEC codes have much better code rates than self-orthogonal DEC codes but slightly worse code rates than existing 2-step majority-logic decodable cyclic DEC codes (2-step cyclic DEC codes). However, parallel decoders of new 2-step DEC codes are much simpler than those of exisiting 2-step cyclic DEC codes, and are nearly as simple as those of 1-step DEC codes.