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[Keyword] GES(423hit)

401-420hit(423hit)

  • Electromagnetic Environments Generated by Power Transmission System

    Seietsu TOMITA  

     
    INVITED PAPER

      Vol:
    E78-B No:2
      Page(s):
    120-126

    Electromagnetic environments generated by power transmission system, possibilities of the interference and its mitigation method was introduced. In the frequency region below 10kHz, concern for DC and AC electric and magnetic field are described. In the frequency range above 10kHz, concern for discharges on power apparatus, electromagnetic emvironments generated by carrier system and fault locating system and passive interference are described. Electromagnetic environment caused by load equipments, that is harmonics, and undesirable electromagnetic emission from power converting units are described finally.

  • Double-Stage Threshold-Type Foreground-Background Congestion Control for Common-Store Queueing System with Multiple Nonpreemptive Priority Classes

    Eiji SHIMAMURA  Iwao SASASE  

     
    PAPER-Communication Theory

      Vol:
    E77-B No:12
      Page(s):
    1556-1563

    The double-stage threshold-type foreground-background congestion control for the common-store queueing system with multiple nonpreemptive priority classes is proposed to improve the transient performance, where the numbers of accepted priority packets in both foreground and background stores are controlled under the double-stage threshold-type scheduling. In the double-stage threshold-type congestion control, the background store is used for any priority packets, and some parts of the background store are reserved for lower-priority packets to accommodate more lower-priority packets in the background store, whereas some parts of the foreground store are reserved for higher-priority packets to avoid the priority deadlock. First, we derive the general set of coupled differential equations describing the system-state, and the expressions for mean system occupancy, throughput and loss probability. Second, the transient behavior of system performance is evaluated from the time-dependent state probabilities by using the Runge-Kutta procedure. It is shown that when the particular traffic class becomes overloaded, high throughputs and low loss probabilities of other priority classes can be obtained.

  • A Note on a Completely Linearly Nested Context-Free Grammar and Its Generalization

    Tetsuo MORITA  

     
    LETTER-Algorithms, Data Structures and Computational Complexity

      Vol:
    E77-A No:12
      Page(s):
    2106-2108

    We introduce a generalized cln grammar (gclng), a generalization of a completely linearly nested context-free grammar (clncfg), of which variables are partitioned linearly and each rule satisfies similar conditions as those of clncfg related to its partition. We show that the class of languages generated by gclng's coincides with the class of quasi-rational languages, and consider the inclusion relations between languages generated by gclng's and those generated by clncfg's.

  • High-Level VLSI Design Specification Validation Using Algorithmic Debugging

    Jiro NAGANUMA  Takeshi OGURA  Tamio HOSHINO  

     
    PAPER

      Vol:
    E77-A No:12
      Page(s):
    1988-1998

    This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

  • A Framework for Feature Extraction of Images by Energy Minimization

    Satoshi NAKAGAWA  Takahiro WATANABE  Yuji KUNO  

     
    PAPER

      Vol:
    E77-D No:11
      Page(s):
    1213-1218

    This paper describes a new feature extraction model (Active Model) which is extended from the active contour model (Snakes). Active Model can be applied to various energy minimizing models since it integrates most of the energy terms ever proposed into one model and also provides the new terms for multiple images such as motion and stereo images. The computational order of energy minimization process is estimated in comparison with a dynamic programming method and a greedy algorithm, and it is shown that the energy minimization process in Active Model is faster than the others. Some experimental results are also shown.

  • Structure Recovery from Multiple Images by Directly Estimating the Intersections in 3-D Space

    Shinjiro KAWATO  

     
    PAPER

      Vol:
    E77-D No:9
      Page(s):
    966-972

    This paper presents a new approach to the recovery of 3-D structure from multiple pairs of images from different viewpoints. Searching for the corresponding points between images, which is common in stereopsis, is avoided. Extracted edges from input images are projected back into 3-D space, and their intersections are calculated directly. Many false intersections may appear, but if we have many pair images, true intersections are extracted by appropriate thresholding. Octree representation of the intersections enables this approach. We consider a way to treat adjacent edge piexels as a line segment rather than as individual points, which differs from previous works and leads to a new algorithm. Experimental results using both synthetic and actual images are also described.

  • Finite State Translation Systems and Parallel Multiple Context-Free Grammars

    Yuichi KAJI  Hiroyuki SEKI  Tadao KASAMI  

     
    PAPER-Automata, Languages and Theory of Computing

      Vol:
    E77-D No:6
      Page(s):
    619-630

    Finite state translation systems (fsts') are a widely studied computational model in the area of tree automata theory. In this paper, the string generating capacities of fsts' and their subclasses are studied. First, it is shown that the class of string languages generated by deterministic fsts' equals to that of parallel multiple context-free grammars, which are an extension of context-free grammars. As a corollary, it can be concluded that the recognition problem for a deterministic fsts is solvable in O(ne1)-time, where n is the length of an input word and e is a constant called the degree of the deterministic fsts'. In contrast to the latter fact, it is also shown that nondeterministic monadic fsts' with state-bound 2 can generate an NP-complete language.

  • Asynchronous and Synchronous Parallel Derivation of Formal Languages

    Katsuhiko NAKAMURA  

     
    PAPER-Automata, Languages and Theory of Computing

      Vol:
    E77-D No:5
      Page(s):
    539-545

    This paper discusses the asynchronous and synchronous parallel derivation of languages based on standard formal grammars. Some of the synchronous languages defined in this paper are essentially equivalent to the languages of E0L and EIL systems. Languages with restrictions on the number of parallel derivation steps are difined so that a t-time language is the set of strings w derived in t(w) or less parallel derivatio steps, where t(n) is an integer function. the properties of asynchronous derivation are generally discussed to clarify their conditions so that the derivation results are independent of the order in which productions are applied. It is shown that: (1) Any context sensitive grammar (CSG) G can be transformed into a CSG G such that the language generated by synchronous derivation in G is equal to that generated by asynchronous derivation in G , and vice versa; (2) Any regular language is a log-time context free language (CFL); (3) The class of CFLs is incomparable with that of log-time CSLs; and (4) If there is a bounded cellular automaton recognizing any language L in time T(n), then L is an O(T(n))-time CSL.

  • Piecewise-Linear Analysis of Nonlinear Resistive Networks Containing Gummel-Poon Models or Shichman-Hodges Models

    Kiyotaka YAMAMURA  

     
    PAPER-Nonlinear Circuits and Systems

      Vol:
    E77-A No:1
      Page(s):
    309-316

    Finding DC solutions of nonlinear networks is one of the most difficult tasks in circuit simulation, and many circuit designers experience difficulties in finding DC solutions using Newton's method. Piecewise-linear analysis has been studied to overcome this difficulty. However, efficient piecewiselinear algorithms have not been proposed for nonlinear resistive networks containing the Gummel-Poon models or the Shichman-Hodges models. In this paper, a new piecewise-linear algorithm is presented for solving nonlinear resistive networks containing these sophisticated transistor models. The basic idea of the algorithm is to exploit the special structure of the nonlinear network equations, namely, the pairwise-separability. The proposed algorithm is globally convergent and much more efficient than the conventional simplical-type piecewise-linear algorithms.

  • Changing Operational Modes in the Context of Pre Run-Time Scheduling

    Gerhard FOHLER  

     
    PAPER

      Vol:
    E76-D No:11
      Page(s):
    1333-1340

    Typical processes controlled by hard real-time computer systems undergo several, mutually exclusive modes of operation. By deterministically switching among a number of static schedules, a pre run-time scheduled system is able to adapt to changing environmental situations. This paper presents concepts for specification of mode changes, construction of static schedules for modes and transitions, and timely run-time execution of mode changes. We propose concepts for mode changes in the context pre run-time scheduled hard real-time systems. While MARS is used to illustrate the concepts' application, they are applicable to a variety of systems. Our methods adhere closely to the ones established for single modes. By decomposing the system into a set of disjoint modes, the design process and its comprehension are facilitated, testing efforts are reduced significantly, and solutions are enabled which do not exist if all system activities of all modes are combined into a single schedule.

  • A Polynomial Time Algorithm for Finding a Largest Common Subgraph of almost Trees of Bounded Degree

    Tatsuya AKUTSU  

     
    PAPER-Algorithms, Data Structures and Computational Complexity

      Vol:
    E76-A No:9
      Page(s):
    1488-1493

    This paper considers the problem of finding a largest common subgraph of graphs, which is an important problem in chemical synthesis. It is known that the problem is NP-hard even if graphs are restricted to planar graphs of vertex degree at most three. By the way, a graph is called an almost tree if E(B)V(B)+ K holds for every block B where K is a constant. In this paper, a polynomial time algorithm for finding a largest common subgraph of two graphs which are connected, almost trees and of bounded vertex degree. The algorithm is an extension of a subtree isomorphism algorithm which is based on dynamic programming. Moreover, it is shown that the degree bound is essential. That is, the problem of finding a largest common subgraph of two connected almost trees is proved to be NP-hard for any K0 if degree is not bounded. The three dimensional matching problem, a well known NP-complete problem, is reduced to the problem.

  • VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis

    P. N. SANKARSHANAN  Hideaki KOBAYASHI  Pankaj KUKKAL  Hiroyuki KANBARA  

     
    PAPER-Hardware Design Languages

      Vol:
    E76-D No:9
      Page(s):
    1055-1065

    This paper presents a description and an analysis of three standard" hardware description languages (HDLs): Very High Speed Integrated Circuit HDL (VHDL), Verilog-HDL, and Unified Design Language for Integrated Circuits (UDL/I), Kyoto University Education Chip (KUE-Chip) is used as a design benchmark to compare the features and syntax of VHDL, Verilog-HDL, and UDL/I.

  • Neural Network Approach to Characterization of Cirrhotic Parenchymal Echo Patterns

    Shin-ya YOSHINO  Akira KOBAYASHI  Takashi YAHAGI  Hiroyuki FUKUDA  Masaaki EBARA  Masao OHTO  

     
    PAPER-Biomedical Signal Processing

      Vol:
    E76-A No:8
      Page(s):
    1316-1322

    We have calssified parenchymal echo patterns of cirrhotic liver into four types, according to the size of hypoechoic nodular lesions. Neural network technique has been applied to the characterization of hepatic parenchymal diseases in ultrasonic B-scan texture. We employed a multi-layer feedforward neural network utilizing the back-propagation algorithm. We carried out four kinds of pre-processings for liver parenchymal pattern in the images. We describe the examination of each performance by these pre-processing techniques. We show four results using (1) only magnitudes of FFT pre-processing, (2) both magnitudes and phase angles, (3) data normalized by the maximum value in the dataset, and (4) data normalized by variance of the dataset. Among the 4 pre-processing data treatments studied, the process combining FFT phase angles and magnitudes of FFT is found to be the most efficient.

  • Super High Definition Image Communications--A Platform for Media Integration--

    Sadayasu ONO  Naohisa OHTA  

     
    INVITED PAPER

      Vol:
    E76-B No:6
      Page(s):
    599-608

    This paper presents a new Hypermedia communication platform supported by the new digital image medium of super high definition (SHD) images. This new image communication platform will encourage the integration of all existing media to realize rich and realistic visual communication over B-ISDN. SHD images have a resolution of more than 20482048 pixels and the frame rate is more than 60 frames/sec. To achieve an real-time compression of SHD moving images, parallel signal processing systems with peak performance of 0.5 Tera Flops will be necessary. The specification requirements, signal processing and communication technologies needed to achieve SHD image communication are discussed. The relationship of hypermedia to SHD images is also examined.

  • Priority Management to Improve the QOS in ATM Networks

    Tien-Yu HUANG  Jean-Lien Chen WU  Jingshown WU  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    249-257

    Broadband ISDN, using asynchronous transfer mode, are expected to carry traffic of different classes, each with its own set of traffic characteristics and performance requirements. To achieve the quality of service in ATM networks, a suitable buffer management scheme is needed. In this paper, we propose a buffer management scheme using a priority service discipline to improve the delay time of delay-sensitive class and the packet loss ratio of loss-sensitive class. The proposed priority scheme requires simple buffer management logic and minor processing overhead. We also analyze the delay time and the packet loss ratio for each class of service. The results indicate that the required buffer size of the proposed priority scheme is reduced and the delay time of each class of service is controlled by a parameter. If the control parameter is appropriately chosen, the quality of service of each class is improved.

  • A Quick Admission Control Strategy Based on Simulation and Regression Approach

    Lung-Sing LIANG  Chii-Lian LIN  Chance DON  Min CHEN  Cheng-Hung HO  Wen-Ruey WU  

     
    PAPER

      Vol:
    E76-B No:3
      Page(s):
    263-269

    This paper proposes a new admission control strategy for ATM networks, which is based on the simulation approach and regression results. Instead of using many traffic descriptors, in our strategy only numbers of connections of different types are needed in performing admission control. The strategy is evaluated from different points of view, real-time, safety, policing and its efficiency which is referred as allowed utilized bandwidth. Since the admission criteria is developed in a form of regression model, the computation of performance for accepting a new connection is quick and easy. Using the confidence region in statistics to represent the admission criteria, a conservative estimation of performance can be achieved. Besides, this strategy is quite independent, thus can be compatible with most policing functions. Finally, its bandwidth utilization is found to be above 0.54. However, the success of this strategy still depends on the reality of input traffic model. Whenever the traffic can be clearly described, the proposed strategy can be easily and precisely applied. Therefore, we also build a traffic model for different type of traffic including constant-bit-rate (CBR), variable-bit-rate (VBR) and bursty traffic. The application of the proposed strategy to different multiplexing schemes, like priority queues and polling system, etc., should be further studied. Considering different level of performance requirement for different type of traffic, which should aid the bandwidth utilization of this strategy, is also an interesting research issue.

  • Transient Analysis of Packet Transmission Rate Control to Release Congestion in High Speed Networks

    Hiroshi INAI  Manabu KATO  Yuji OIE  Masayuki MURATA  Hideo MIYAHARA  

     
    PAPER

      Vol:
    E75-B No:12
      Page(s):
    1354-1366

    Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

  • Thrashing in an Input Buffer Limiting Scheme under Various Node Configurations

    Shigeru SHIMAMOTO  Jaidev KANIYIL  Yoshikuni ONOZATO  Shoichi NOGUCHI  

     
    PAPER

      Vol:
    E75-B No:12
      Page(s):
    1327-1337

    This paper is a study on the behavioral aspects of the input buffer limiting scheme whose basic feature is to award priority to the transit messages over the input messages so that congestion does not develop in the network. The numerical method employed in the analysis is that proposed in Ref.(7). The performance aspects are studied for different buffer capacities, different message handling capacities and different levels of reservation for transit traffic. The numerical method indicates that thrashing occurs at low levels of reservation for the transit messages, irrespective of the buffer size or the processor capacities of the node. This observation is supported by simulation results. With reference to the state-space of the model of our study, the congestion aspects are related to two Liapunov functions. Under the domain of one of the Liapunov functions, the evolution of the perturbed system is towards a congested state whereas, under the domain of the other Liapunov function, the evolution is towards a congestion-free state. Regardless of the configuration, it is found that the fundamental characteristic of the congestion under the input buffer limiting scheme is the characteristic of a fold catastrophe. In the systems with insufficient level of reservation for the transit traffic, the performance degradation appears to be inevitable, irrespective of the capacities of the nodal processor and output channel processor, and the size of the buffer pool. Given such an inevitability, the active life of a node under a typical node configuration is studied by simulation. A suitable performance index is suggested to assess the performance of deadlock-prone nodes.

  • Verification of Register Transfer Level (RTL) Designs

    Alberto Palacios PAWLOVSKY  Sachio NAITO  

     
    PAPER

      Vol:
    E75-D No:6
      Page(s):
    785-791

    This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

  • Rete-Based Congestion Control in High Speed Packet-Switching Networks

    Hiroshi INAI  Yuji KAMICHIKA  Masayuki MURATA  Hideo MIYAHARA  

     
    PAPER-Communication Networks and Service

      Vol:
    E75-B No:11
      Page(s):
    1199-1207

    Rate-based congestion/flow control is a promising way to achieve high throughput in high speed packet-switching networks. We consider a rate-based congestion control to aim at obtaining high throughput and fair sharing of the communication resources. In the scheme, each intermediate node informs its congestion status to the source node. Two kinds of control packets are used for this mechanism. One (a choke packet) is to throttle the rate and another (a loosen packet) is to allow increase of the rate. The source node initiates transmission with a low rate and increases the rate slowly to avoid a rapid increase of the packet queueing at an intermediate node. When the source node receives a choke packet, it decreases the rate rapidly to relieve congestion as soon as possible. The source node upon receipt a loosen packet increases the rate slowly again. We develop a queueing model to investigate the parameter settings to provide a good performance via simulation. The increasing and decreasing parameters of the rate control function are first investigated in various load conditions. We next examine the effect of the queue-length threshold value for the indication of congestion at the intermediate node. The numerical results indicate that the threshold value should be small to obtain a good performance. We finally introduce a technique which accurately recognizes congestion and inhibits an acceptable queueing of the packets at intermediate nodes.

401-420hit(423hit)