This paper presents a deep neural network (DNN) based symbol detection and modulation classification detector (SDMCD) for mixed blind signals detection. Unlike conventional methods that employ symbol detection after modulation classification, the proposed SDMCD can perform symbol recovery and modulation identification simultaneously. A cumulant and moment feature vector is presented in conjunction with a low complexity sparse autoencoder architecture to complete mixed signals detection. Numerical results show that SDMCD scheme has remarkable symbol error rate performance and modulation classification accuracy for various modulation formats in AWGN and Rayleigh fading channels. Furthermore, the proposed detector has robust performance under the impact of frequency and phase offsets.

We propose a novel decoding algorithm called “sampling decoding”, which is constructed using a Markov Chain Monte Carlo (MCMC) method and implements Maximum a Posteriori Probability decoding in an approximate manner. It is also shown that sampling decoding can be easily extended to universal coding or to be applicable for Markov sources. In simulation experiments comparing the proposed algorithm with the sum-product decoding algorithm, sampling decoding is shown to perform better as sample size increases, although decoding time becomes proportionally longer. The mixing time, which measures how large a sample size is needed for the MCMC process to converge to the limiting distribution, is evaluated for a simple coding matrix construction.

The notion of multiple constant multiplication (MCM) is extensively adopted in digital signal processing (DSP) applications such as finite impulse filter (FIR) designs. A set of adders is utilized to replace regular multipliers for the multiplications between input data and constant filter coefficients. Though many algorithms have been proposed to reduce the total number of adders in an MCM block for area minimization, they do not consider the actual bitwidth of each adder, which may not estimate the hardware cost well enough. Therefore, in this article we propose a bitwidth-aware MCM optimization algorithm that focuses on minimizing the total number of adder bits rather than the adder count. It first builds a subexpression graph based on the given coefficients, derives a set of constraints for adder bitwidth minimization, and then optimally solves the problem through integer linear programming (ILP). Experimental results show that the proposed algorithm can effectively reduce the required adder bit count and outperforms the existing state-of-the-art techniques.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.

In order to realize Integrated Circuits (IC) with operation over the 10 GHz range, conventional CMOS logic faces critical issues, such as increasing power consumption, and difficulty to aggressively scale the device size and so on. To overcome this issue, we have proposed Current Controlled-MOS Current Mode Logic (CC-MCML) to realize the reduction of power consumption and the enhancement of the operation speed in logic circuits without scaling the gate length of the MOSFET, and confirmed the performance of these circuits both theoretically and experimentally. In the CC-MCML it is extremely important to control the input voltage of the MOSFET used as the constant current source in order to make the base voltage of the input signal and the output signal equivalent. In this paper, we propose CC-MCML/MTJ (Magnetic Tunnel Junction) circuit, which is one type of nonvolatile memory hybrid circuit technology. A more stable and precise operation is realized by cutting the range of the input voltage of the constant current source, and it is shown that the operation of CC-MCML/MTJ Hybrid Circuit enables us to suppress the base voltage difference due to the Vth fluctuation in comparison with the conventional CC-MCML. These results imply the high potential of Si-CMOS/Spintronics Hybrid technologies for future IC.

A new type of modulation called continuous-phase parallel-combinatory high-compaction multicarrier modulation (CPPC/HC-MCM) is proposed. CPPC/HC-MCM employs the technique of continuous-phase modulation (CPM) and avoids the formation of amplitude gaps between two successive signals to enhance the spectral efficiency of conventional PC/HC-MCM. Results of simulations show that CPPC/HC-MCM is spectrally efficient and achieves a smaller bit error rate than conventional (unmodulated) PC/HC-MCM at a common spectral efficiency even if the peak-to-average power ratio is considered.

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

It is well known that the performance of CDMA systems may degrade in the presence of spreading code mismatch. The diagonal loading multiple constrained minimum variance (DL-MCMV) approaches have been proposed to deal with the mismatch problem. However, they still cannot improve the robust capability efficiently due to the spreading code mismatch. In this letter, a detector based on the variable DL technique is presented that offers more robust capabilities than the MCMV and DL-MCMV detectors. Computer simulation results are provided that illustrate the effectiveness of the proposed detector.

In this paper, we propose the novel Dynamic Feedback (DF-) MCML technique for high-speed and high-gain MCML type latch. The concept of the proposed DF-MCML technique is as follows; the output node signal is feedbacked to the input node in Sampling-Mode, and the output node is opened from the input node in Holding-Mode. It is shown by analytic theory that by this dynamic feedback sequence, both stability and sensibility of latch in Sampling-Mode is exponentially improved, and the gain of latch in Holding-Mode is drastically increased. Finally, we have numerically investigated the circuit performance of the novel DF-MCML type latch in comparison with the conventional MCML type latch by using P-Spice simulator. The maximum operation frequency of 180 nm DF-MCML type latch reaches over 20 GHz that is 2 times than the conventional MCML type latch. It is made clear that the proposed novel Dynamic Feedback MCML technique is suitable for over 10 GHz high-speed and high-gain Si ULSIs.

In this comment we point out that the mapping from carry-propagation adders to carry-save adders in the context of shift-and-add multiplication is inconsistent. Based on this it is shown that the implementation in Ref.[1] does not achieve any complexity reduction in practice.

In this paper, we propose a new modulation named parallel combinatory/high compaction multi-carrier modulation (PC/HC-MCM) using the techniques of parallel combinatory orthogonal frequency division multiplexing (PC-OFDM) and high compaction multi-carrier modulation (HC-MCM). Two types of PC/HC-MCM systems, which are named as modulated PC/HC-MCM system and (unmodulated) PC/HC-MCM system, can be designed. The modulated PC/HC-MCM system achieves better bit-error rate (BER) performance than that of HC-MCM system with equal bandwidth efficiency (BWE). The PC/HC-MCM system can obtain the better peak-to-average power ratio (PAPR) characteristics by selecting appropriate constellation for each subcarrier. On the other hand, since PC/HC-MCM can divide the PC-OFDM symbol duration into multiple time-slots, the advantages of frequency hopping (FH) can be applied in the PC/HC-MCM system. Therefore, we also combine the PC/HC-MCM and frequency hopping multiple access (FHMA) to propose a novel multiple access (MA) system. It can simultaneously transmit multiple users' data within one symbol duration of PC-OFDM.

This paper presents the implementation of a 31-tap FIR Hilbert transform digital filter chip used in the digital-IF receivers, to confirm the effectiveness of our new design method. Our design method that we previously reported is based on a computation sharing multiplier using a new horizontal and vertical common subexpression techniques. A 31-tap FIR Hilbert transform digital filter was implemented and fabricated in 0.35 µm CMOS standard cell library. The chip's core contains approximately 33k transistors and occupies 0.86 mm2. The chip also has an operating speed of 70 MHz over. The implementation results show that the proposed Hilbert transformer has a smallest cost factor and so that is a high performance filter.

Recent advances in 77-GHz MMIC module design techniques for automotive radar applications are reviewed in this paper. The target of R&D activities is moving from high performance to low cost, mass production, high-yield manufacturing and testing. To meet the stringent requirements, millimeter-wave module design techniques have made significant progress especially in packaging, bonding, and making interface with other modules. In addition, millimeter-wave semiconductor devices and MMICs have made remarkable improvements for low cost and mass production. In this paper, the topics focusing on millimeter-wave semiconductor devices and 77-GHz MMICs are reviewed first. Then the recent R&D results on 77-GHz MMIC module design techniques are introduced, showing the technical trend of packaging, bonding, and making interface with other modules for millimeter-wave, highly-integrated, low-cost MMIC modules. Finally, the existing and future module design issues for automotive radar applications are discussed.

Motion capture technology is widely used to make a realistic motion in these days. Different motion capture devices use different motion capture data formats. Because of the lack of compatibility of motion capture data animators can't reuse the already captured motion sequence. In addition, it is difficult for integrating, storing and retrieving motion capture data with different formats in the storage. In this paper, we propose a standard format for integrating a different motion capture data formats. In addition, we propose a framework of a system that manages motion capture data using our standard format. Our standard format is called MCML (Motion Capture Markup Language). It is a markup language for motion capture data and is based on XML (extensible Markup Language). Our system designed to manage motion capture data consists of a several components -- Mocap Syntax Analyzer, MCML Converter, MCML Editor, Motion Viewer, MCML Storage Wrapper.

In this paper, we propose a new counting scheme for m n contingency tables. Our scheme is a modification of Dyer and Greenhill's scheme for two rowed contingency tables. We can estimate not only the sizes of error, but also the sizes of the bias of the number of tables obtained by our scheme, on the assumption that we have an approximate sampler.

We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic and optoelectronic devices. Due to their characteristics of low surface tension, however, the parametric design guidelines are necessary for resin self-alignment capability. In this paper, a shape prediction mathematical model and a numerical method are developed. The developed system is capable of achieving the liquid joint geometry and the parametric design for self-alignment capability. The influences of geometric parameters such as liquid volume, component weight, pad radius, liquid surface tension on the shape of liquid joint are investigated. Furthermore, the parametric design guidelines considered the process-related practical matters of misalignment level, distribution of the supplied liquid volumes and coplanarity deviation includes difference of the height between the pads are provided.

With the progress of the electronics industry and radio communication technology, humans enjoy greater freedom in communicating. On the other hand, certain problems, such as electromagnetic interference (EMI), have arisen due to the increased use of electromagnetic (EM) waves. EM wave absorbers are used for constructing an anechoic chamber to test and measure EMI and electromagnetic susceptibility (EMS). Prior to 1998, international standards for anechoic chambers required that EM wave absorbers should absorb more 20 dB in the bandwidth from 30 MHz to 1,000 MHz. Since November 1998, however, the Comit International Special des Perturbations Radioelectrigne (CISPR) has required that the frequency bandwidth be extended from 1 GHz to 18 GHz for EMI measurement by the CISPR11. In this work, wide-band EM wave absorbers were designed by a theoretical model using the equivalent material constants method (EMCM). We designed a cross-shaped absorber which has a bandwidth from 30 MHz to above 2 GHz under the tolerance limit of -20 dB in reflection, the results of which were compared with the results analyzed using the finite-difference time-domain method (FDTD). The tapered cross-shaped absorber was also designed, which has a bandwidth from 30 MHz to 26 GHz under the same tolerance limit.

A novel self-alignment process using the surface tension of the liquid resin for assembly of electronic or optoelectronic devices in 3-D space has been proposed. The vertical alignment can be controlled by using of metal sphere, reducing the necessary precise process control such as solder volumes and external forces, and allowing large tolerances in liquid volume and misalignment. Lateral alignment could be also achieved by making the liquid resin constrained on the 3-dimensional pads on chip and substrate. This study focused on the principle of self-alignment and final alignment accuracy. In addition, the possibility of self-alignment process was verified by analytic numerical method and scaled-up experiment. An average alignment accuracy of less than 0.25 µm has been obtained. It is thought that this process is effective for assembly simply at low process temperature, low cost and without flux in future assembly techniques.

We have developed a novel self-alignment process using the surface tension of the liquid resin for assembly of electronic or optoelectronic devices. Though the liquid resins have a characteristics as low as one tenth of the surface tension of solder in general, restoring forces for self-alignment capability can be produced by making it constrained on the 3-dimensional pads on chip and substrate. In this paper, its principle and characteristics are described and the relationship between process parameters and joint geometry were examined. And the possibility of self-alignment process was verified by analytic numerical method and scaled-up experiment. A self-alignment accuracy was examined experimentally and show that it became less than 0.4 µm. It can provide a useful information on various parameters involved in joint geometry and optimal design guideline to generate the proper profiles.