A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

We have developed a Field-Programmable Multi-Chip Module (FPMCM) whose component is the telecommunication-oriented FPGAs, called PROTEUS. The module consists of 3 3 PROTEUS FPGAs and its size is 114 mm square. Each PROTEUS chip is mounted on the MCM substrate using Tape Automated Bonding (TAB) technology so as to minimize the size of the MCM and the production cost. The interconnection topology among the FPGAs is a simple mesh. However, the connection can be changed logically, because PROTEUS itself has a special inter-I/O bypass resource in it. Using this mechanism, the interchip connection delay can be reduced without sacrificing the flexibility, compared to the previous FPMCM implementation using some other interconnection switches which often have a large propagation delay. The interchip connection delay is 200 ps. We have also developed a rapid prototyping system comprising several MCMs, and implemented telecommunication circuits in it.

This paper describes advanced ATM switching system hardware that uses a high-performance and cost-effective MCM-D module as an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size is reduced to 50. 8 mm 50. 8 mm. This is 40% of that (100 mm 65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with a high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module is mounted on an ATM line interface circuit, and realizes 150 Mbit/s throughput ATM-layer functions (header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to advanced ATM switching systems.

In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subexpressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.

This paper explores the potential of multiwave interconnectionsoptical interconnections that employ wavelength components as multiplexable information carriersfor constructing next-generation multiprocessor systems using MCM technology. A hypercube-based multiprocessor network called the multiwave hypercube (MWHC) is proposed, where multiwave interconnections provide highly-flexible dynamic communication channels among processing elements. A performance analysis shows that the use of multiwavelength optics makes possible the reduction of network complexity on an MCM substrate, while supporting low-latency message routing.

This paper describes a high-density, high-pin-count flexible SMD connector used for high-speed data buses between MCMs or daughter boards. This connector consists of a flexible film cable interconnection with accurately controlled characteristic impedance, and a contact housing composed of double-line contacts and SMD type leads. It has 98 contacts each with a pitch of 0.4 mm. The connector mounting area is 6 mm wide and 23 mm long. The flexible cable has a double-sided triple-parallel micro stripline structure with an insertion force of less than 2.9 kgf and characteristic impedance of 48 to 50 Ω. Insertion loss is -0.5 dB at 600 MHz and crosstalk noise is less than 110 mV at 250 ps rising time. This connector can be used for high-speed data transmission of up to 300 ps rising time.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.