This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.

This paper discusses the design, implementation, and performance of a bus-connected multiprocessor, called Presto, for a Rete-based production system. To perform a match, which is a major phase of a production system, a Presto match scheme exploits the subnetworks that are separated by the top two-input nodes and the token flow control at these nodes. Since parallelism of a production system can only increase speed 10-fold, the aim is to do so efficiently on a low-cost, compact bus-connected multi-processor system without shared memory or cache memory. The Presto hardware consists of up to 10 processisng elements (PEs), each comprising a commercial microprocessor, 4 Mbytes of local memory, and two kinds of newly developed ASIC chips for memory control and bus control. Hierarchical system software is provided for developing interpreter programs. Measurement with 10 PEs shows that sample programs run 5-7 times faster.

This paper reviews the capability of the three layer neural network (TLNN) with one output neuron. The input set is restricted to a finite subset S of En, and the TLNN implements a function F such as F : S I={1, -1}, i,e., F is a dichotomy of S. How many functions (dichotomies) can it compute by appropriately adjusting parameters in the TLNN? Brief historical review, some theorems on the subject obtained so far, and related topics are presented. Several open problems are also included.

The encoding of high quality and super high definition images requires new approaches to the coding problem. The nature of such images and the applications in which they are used prohibits the introduction of perceptible degradation by the coding process. In this paper, we discuss techniques for the perceptually transparent coding of images. Although technically lossy methods, images encoded and reconstructed using these techniques appear identical to the original images. The reconstructed images can be postprocessed (e.g., enhanced via anisotropic filtering), due to the absence of structured errors, commonly introduced by conventional lossy methods. The compression, ratios obtained are substantially higher than those achieved using lossless means.

A closure test MCT (meet-in-the-middle closure test) has been introduced to analyze the algebraic properties of cryptosystems. Since MCT needs a large amount of memory, it is hard to implement with an ordinary meet-in-the-middle method. As a feasible version of MCT, this paper presents a switching closure test SCT based on a new memoryless meet-in-the-middle method. To achieve the memoryless method, appropriate techniques, such as expansion of cycling detection methods for one function into a method for two functions and an efficient intersection search method that uses only a small amount of memory, are effectively used.

Lingas developed an NC algorithm for subgraph isomorphism for connected graphs of bounded separator and bounded valence. We present an NC algorithm for computing canonical forms of graphs of bounded separator by using the similar technique.

This paper proposes a designing algorithm for quadrilateral recursive filters which consist of four quarter-plane filters in the four quadrants. This can realize a perfect zero-phase filtering which is essential for image processing. Furthermore, several parallel processing algorithms capable of performing under very high parallel efficiency are developed on line-connected and mesh-connected processor arrays. By these proposals, the advantage of two-dimensional non-causal zero-phase recursive digital filters is made clear.

This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n2) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.

This paper discusses the trends and future issues in hardware description languages (HDL's) and high-level synthesis systems. First the importance of HDL's and high-level synthesis is described. Then, several HDL's and related CAD systems are briefly introduced. Finally, the requirements to future HDL's and highlevel synthesis systems are discussed from several points of view.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

In general, dynamic channel assignment has a better performance than fixed channel assignment in a cellular mobile communication system. However, it is complex to control the system and a lot of equipments are required in each cell when dynamic channel assignment is applied to a large service area. Therefore, it is effective to limit the size of the service area in order to correct the defects of dynamic channel assignment. So, we propose an application of dynamic channel assignment to a part of a service area when fixed channel assignment is applied to the remaining part of the area. In the system, the efficiency of channel usage in some cells sometimes becomes terribly low. The system has such a problem to be improved. We show that the rearrangement of the channel allocation is effective on the problem.

The aim of this article is to show the effectiveness of exploiting separability in numerical analysis of nonlinear systems. Separability is a valuable property of nonlinear mappings which appears with surprising frequency in science and engineering. By exploiting this property, computational complexity of many numerical algorithms can be substantially improved. However, this idea has not been received much attention in the fields of electronics, information and communication engineerings. In recent years, efficient algorithms that exploit the separability have been proposed in the areas of circuit analysis, homotopy methods, integer labeling methods, nonlinear programming, information theory, numerical differentiation, and neural networks. In this article, these algorithms are surveyed, and it is shown that considerable improvement of computational efficiency can be achieved by exploiting the separability.

This work describes a new analytical MOSFET model for analog circuit simulation based on the charge-sheet model. The current equation consists of diffusion and drift components, therefore Ids is a smooth function of the applied voltages. Since the original charge-sheet model is valid only for long-channel transistors, it has been further developed to describe quarter-micron MOSFETs by introducing the lateral electric field Ey into the theory. The new model includes these field contributions self-consistently, and describes the drain current of MOSFETs from long to quarter-micron channel lengths with a single model parameter set without discontinuities in derivatives of the drain current Ids. The mobility reduction due to Ey is described by an empirical equation with physical parameter values taken from literature. Only two fitting parameters, the impurity scattering and the surface roughness scattering in the mobility equation, are added to the physical parameters. The subdiffusion lengths are also taken as fitting parameters. Though the new model reduces the number of fitting parameters totally to four, it reproduces measured Ids excellently for MOSFETs with all channel lengths. The model has been included in the parameter extraction program JANUS, which extracts model parameters automatically. The algorithm for parameter extraction is summarized.

Binaural effects in two measures are studied. One measure is the detectable limen of click sounds under lateralization of diotic or dichotic noise signals, and the other is phoneme articulation score under localization or lateralization of speech and noise signals. The experiments use a headphones system with listener's own head related transfer function (HRTF) filters. The HRTF filter coefficients are calculated individually from the impulse responses due to the listener's HRTF measured in a slightly sound reflective booth. The frequency response of the headphone is compensated for using an inverse filter calculated from the response at the subject's own ear canal entrance point. Considering the speech frequency band in tele-communication systems is not sufficiently wide, the bandwidth of the HRTF filter is limited below 6.2 kHz. However, the experiments of the localization simulation in the horizontal plane show that the sound image is mostly perceived outside the head in the simulated direction. Under simulation of localization or lateralization of speech and noise signals, the phoneme articulation score increases when the simulation spatially separates the phonemes from the noise signals while the total signal to noise ratio for both ears is maintained constant. This result shows the binaural effect in speech intelligibility under the noise disturbance condition, which is regarded as a part of the cocktail party effect.

Physical optics (PO) have been extensively used in radiation pattern analysis of offset parabola. Physical Theory of Diffraction (PTD) proposed later has better accuracy. This paper presents an analytical/numerical comparative study of these methods to demonstrate the limitations of PO. PO envelope errors in co-polar patterns are expressed as functions of antenna parameters. Serious PO errors in cross polarization prediction are pointed out for antennas with cross-polar suppressing feeds polarized in the plane of asymmetry.

By adding some functions to memories, highly parallel computation may be realized. We have proposed memory-based parallel computation models, which uses a new functional memory as a SIMD type parallel computation engine. In this paper, we consider models with communication between the words of the functional memory. The memory-based parallel computation model consists of a random access machine and a functional memory. On the functional memory, it is possible to access multiple words in parallel according to the partial match with their memory addresses. The cube-FRAM model, which we propose in this paper, has a hypercube network on the functional memory. We prove that PSPACE is accelerated to polynomial time on the model. We think that the operations on each word of the functional memory are, in a sense, the essential ones for SIMD type parallel computation to realize the computational power.

A maximal l-diameter tree cover of a graph G(V,E) is a spanning subgraph C(V,EC) of G such that each connected component of C is a tree, C contains no path with more than l edges, and adding any edge in EEC to C yields either a path of length l1 or a cycle. For every function f from positive integers to positive integers, the maximal f-diameter tree cover prolem (MDTC(f) problem for short) is to find a maximal f(n)-diameter tree cover of G, given an n-node graph G. In this paper, we give two parallel algorithms for the MDTC(f) problem. The first algorithm can be implemented in time O(TMSP(n,f(n))log2n) using polynomial number of processors on an EREW PRAM, where TMSP(n,f(n) is the time needed to find a maximal set of vertex disjoint paths of length f(n) in a given n-node graph using polynomial number of processors on an EREW PRAM. We then show that if suitable restrictions are imposed on the input graph and/or on the magnitude of f, then TMSP(n,f(n))O(logkn) for some constant k and thus, for such cases, we obtain an NC algorithm for the MDTC(f) problem. The second algorithm runs in time O(n log2n/{f(n)1}) using polynomial number of processors on an EREW PRAM. Thus if f(n)Ω(n/logkn) for some kO, we obtain an NC algorithm for the MDTC(f) problem.

This paper investigates the performance of the line spectrum pair (LSP) frequency parameter representation for speech recognition. Transitional parameters of LSP frequencies are defined using first-order regression coefficients. The transitional and the instantaneous frequency parameters are linearly combined to generate a single feature vector used for recognition. The performance of the single vector is compared with that of the cepstral coefficients (CC) representation using a minimumdistance classifier in speaker-independent isolated word recognition experiments. In the speech recognition experiments, the transitional and the instantaneous coefficients are also combined in the distance domain. Also, inverse variance weighted Euclidean measures are defined using LSP frequencies to achieve Mel-scale-like warping and the new warped-frequencies are used in recognition experiments. The performance of the single feature vector defined with transitional and instantaneous LSP frequencies is found to be the best among the measures used in the experiments.

Transmittance distribution along a horizontal line in LCDs addressed by amorphous silicon TFTs was investigated using measurements and calculations. Nonuniformity of the distribution, in which the transmittance increased with increasing distance from the left edge of the LCD, was observed in a 10 inch diagonal TFT-LCD. The cause of the nonuniformity was attributed to the decrease in voltage drop due to the gate source parasitic capacitance and the increase in gate voltage fall time due to large line resistance, based on the measurements of voltage drops in TFT test elements and calculations considering the decrease in voltage drop. The distribution could be improved by reducing the line resistance and parasitic capacitance in the actual LCD.

We study the depth of planar Boolean circuits. We show that planar Boolean circuits of depth D(n) are simulated by on-line Turing machines in space O(D(n)). From this relationship, it is shown that any planar circuit for computing integer multiplication requires linear depth. It is also shown that a planar analogue to the NC-hierarchy is properly separated.