Our goal is to realize an extra-large stereoscopic display in the open air for use by the general public. We have developed a stereoscopic large display by use of a full-color LED panel. Although the developed display enables viewers to view the stereoscopic images without any special glasses, it is necessary for the viewers to move to stand within the viewing areas. Movements of the viewers are considered to depend on arrangements of viewing areas. The purpose of this paper is to investigate the movements of viewers who watch different designs of stereoscopic LED displays with a parallax barrier, including conventional designs to provide multiple perspective images and designs to eliminate pseudoscopic viewing areas, and evaluate the performance of different viewing areas based on the obtained paths of the viewers. We have developed a real-time measurement system of a viewer's position by use of a camera on the ceiling. We have recorded the viewing movements caused by the shift of viewing areas. It was found that the viewers moved to stand on orthoscopic viewing positions. The movements of viewers who move to find a viewing area have been recorded with different designs of stereoscopic LED displays that provide different viewing areas. We have calculated the lateral moving time of the viewers'movements. It is shown that the elimination of pseudoscopic viewing areas reduces the lateral moving time. Thus, the real-time measurement system of a viewer's position has been utilized for evaluation of performance of the different designs of stereoscopic LED displays.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

This paper presents a multi-resolution optical flow estimation method that is robust against large variation in the estimation parameter. For each level solution of the multi-grid estimation, a nonlinear iteration is proposed differently from the existing method, where the incremental displacement from the coarser level optical flow is calculated by linear iteration. The experimental results show that the proposed scheme has better error-performance in a much wider range of regularization parameters.

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 pq), a vertical (pq 1) or a block (p q) subarray with a constant interval in an arbitrary position in an M N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

We develop an algorithm for a controller design method for Max-Plus Linear (MPL) systems with selective parameters. Since the conventional algorithm we proposed requires high computational load when the prediction horizon is large, two methods for reducing the calculation time are proposed. One is based upon the branch-and-bound method, and the other is to reuse the optimal solution. The effectiveness of these two methods is confirmed through numerical simulation.

A reaction-diffusion computer is a large-scale array of elementary processors, micro-volumes of chemical medium, which act, change their states determined by chemical reactions, concurrently and interact locally, via local diffusion of chemical species; it transforms data to results, both represented by concentration profiles of chemical species, by traveling and colliding waves in spatially extended chemical media. We show that reaction-diffusion processors, simulated or experimental, can solve a variety of tasks, including computational geometry, robot navigation, logics and arithmetics.

This paper presents a voltage-mode WTA/MAX circuit that achieves high-speed and multi-chip features. Based on the efficient averaged-value comparison approach, the time and hardware complexities are proportional to O(log N) and O(N) respectively, where N is the number of inputs. In addition, a voltage comparison element (VCE) circuit is proposed to achieve multi-chip function. In the proposed circuit, the averaged-value calculator is built using resistor array that prevents the matching problem of transistor array. The whole circuit was fabricated with the TSMC 0.35 µm signal-poly quadruple-metal CMOS process. With eight input signals, the measurement results show that the proposed circuit resolved input voltages differing by 10 mV in 30 ns, and the multi-chip capability was also verified.

Estimating the parameters of a statistical distribution from measured sample values forms an essential part of many signal processing tasks. K-distribution has been proven to be an appropriate model for characterising the amplitude of sea clutter. In this paper, a new method for estimating the parameters of K-Distribution is proposed. The method greatly lowers the computational requirement and variance of parameter estimates when compared with the existing non-maximum likelihood methods.

In this paper we propose an inter-block evaluation method to further reduce evaluation numbers in GA-based image halftoning technique. We design the algorithm to avoid noise in the fitness function by evolving all image blocks concurrently, exploiting the inter-block correlation, and sharing information between neighbor image blocks. The effectiveness of the method when the population and image block size are reduced, and the configuration of selection and genetic operators are investigated in detail. Simulation results show that the proposed method can remarkably reduce the entire evaluation numbers to generate high quality bi-level halftone images by suppressing noise around block boundaries.

Efficient general secure multiparty computation (MPC) protocols were previously proposed, and the combination with the efficient auction circuits achieves the efficient sealed-bid auctions with the full privacy and correctness. However, the combination requires that each bidder submits ciphertexts of bits representing his bid, and their zero-knowledge proofs. This cost amounts to about 80 multi-exponentiations in usual case that the bid size is 20 bits (i.e. about 1,000,000 bid prices). This paper proposes sealed-bid auction protocols based on the efficient MPC protocols, where a bidder can submit only a single ciphertext. The bidder's cost is a few multi-exponentiations, and thus the proposed protocols are suitable for mobile bidders. A novel technique for the realization is a bit-slicing conversion by multiple servers, where a single ciphertext for a bid is securely converted into ciphertexts of bits representing the bid.

Density evolution has recently been used to analyze the iterative decoding of Low Density Parity Check (LDPC) codes, Turbo codes, and Serially Concatenated Convolutional Codes (SCCC). The density evolution technique makes it possible to explain many characteristics of iterative decoding including convergence of performance and preferred structures for the constituent codes. While the analytic density evolution methods were applied to LDPC codes, the simulation based density evolution methods were used for Turbo codes and SCCC due to analytic difficulties. In this paper, several density evolution ideas in the literature are used to analyze common code structures and it is shown that those ideas yield consistent results. In order to do that, we derive expressions for density evolution of SCCC with a simple 2-state constituent code. The analytic expressions are based on the sum-product and min-sum algorithms, and the thresholds are evaluated for both message passing algorithms. Particularly, for the min-sum algorithm, the density evolution with Gaussian approximation is derived and used to analyze the effect of scaling soft information. The scaling of extrinsic information slows down the convergence of soft information or avoids an overestimation effect of it and results in better performance, and its gain is maximized in particular constituent codes. Similar approaches are made for LDPC code. We show that the scaling gain is noticeable in the LDPC code as well. This scaling gain is analyzed with both density evolution and simulation performance. The expected scaling gain by density evolution matches well with the achievable scaling gain from simulation results. These results can be extended to the irregular LDPC codes based on the degree distribution for the min-sum algorithm. All density evolution algorithms used in this paper are based on the Gaussian approximation for the exchanged messages.

When we try to solve Multiobjective Optimization Problems (MOPs) using an evolutionary algorithm, the Pareto Genetic Algorithm (Pareto GA) introduced by Goldberg in 1989 has now become a sort of standard. After the first introduction, this approach was further developed and lead to many applications. All of these approaches are based on Pareto ranking and use the fitness sharing function to maintain diversity. On the other hand in the early 50's another scheme was presented by Nash. This approach introduced the notion of Nash Equilibrium and aimed at solving optimization problems having multiobjective functions that are originated from Game Theory and Economics. Since the concept of Nash Equilibrium as a solution of these problems was introduced, game theorists have attempted to formalize aspects of the equilibrium solution. The Nash Genetic Algorithm (Nash GA), which is introduced by Sefrioui, is the idea to bring together genetic algorithms and Nash strategy. The aim of this algorithm is to find the Nash Equilibrium of MOPs through the genetic process. Another central achievement of evolutionary game theory is the introduction of a method by which agents can play optimal strategies in the absence of rationality. Not the rationality but through the process of Darwinian selection, a population of agents can evolve to an Evolutionary Stable Strategy (ESS) introduced by Maynard Smith in 1982. In this paper, we propose Game theory based Co-Evolutionary Algorithm (GCEA) and try to find the ESS as a solution of MOPs. By applying newly designed co-evolutionary algorithm to several MOPs, the first we will confirm that evolutionary game can be embodied by co-evolutionary algorithm and this co-evolutionary algorithm can find ESSs as a solutions of MOPs. The second, we show optimization performance of GCEA by applying this model to several test MOPs and comparing with the solutions of previously introduced evolutionary optimization algorithms.

A bandpass filter (BPF) with shielded inverted microstrip lines (SIMSL), previously demonstrated by the author, has shown the nontrivial asymmetry of filter responses in spite of adopting a conventional filter synthesis procedure. This paper will reveal the mechanism of the asymmetry and propose prescriptions for recovering the defect, in addition to observing the wave propagation property of SIMSL. Firstly, the behavior of phase constants or effective dielectric constants for various modes propagating on single SIMSL are indicated in terms of the line configuration, and the dispersion characteristics of the quasi-TEM mode are interpreted from the point of mode coupling between the pure TEM mode and dielectric slab modes. Then it is shown that the asymmetry is dependent only on the transmission characteristics of SIMSL parallel-coupled lines involved in the filter circuits. Theoretical considerations reveal that the asymmetry is due to the fact that SIMSL has quite different phase constants for the even- and odd-mode. On the basis of these results, the optimized BPF is designed and it is experimentally demonstrated that the symmetry of its responses is notably recovered. Furthermore, this optimization is still quite efficient for achieving high attenuation properties at its harmonics.

In this paper, we propose a partial erasure decoding scheme with erasure-decision threshold for Reed-Solomon (RS) codes and analyze its performance in frequency-hopped multiple-access communications. RS code is used to correct erasures and errors caused by other-user interference. Binary FSK is employed to transmit the channel symbol. The proposed decoder decides whether to erase the received RS code symbol based on the ersure decsion threshold. The approximated formula for optimal erasure decision threshold is derived in such a way that packet error probability can be minimized. Numerical results show that the employment of adaptive erasure decision threshold attains the higher normalized throughput in the areas of high channel traffic cases.

In this letter, we show the effects of the chip waveform selection on the detection performance of the energy detector in DS/SS communications. Three chip waveforms such as rectangular, half-sine and raised-cosine are examined as the DS/SS chip waveform. It is demonstrated that the partial-band detection can enhance the detection performance of the energy detector approximately 50-70% compared with the full-band detection. When the chip rate is identical, the raised-cosine waveform shows lower detection probability due to its wider spreading bandwidth. However, when the spreading bandwidth is identical, the rectangular waveform shows lower detection probability due to its lower partial-band energy factor.

This paper presents a new approach based on current mode circuits for fast and accurate optical level monitoring with wide dynamic range of a gigabit burst-mode laser driver chip. Our proposed solution overcomes the drawbacks that voltage mode implementations show at higher bit rates or in other technologies. The main speed-limiting factor of the level monitoring circuitry is the parasitic capacitance of the back facet monitor photodiode. We propose the use of an active-input current mirror to reduce the impact of this parasitic capacitance. The mirror produces two copies of the photo current, one to be used for the "0" level measurement and another for the "1" level measurement. The mirrored currents are compared to two reference currents by two current comparators. Every reference current needs only one calibration at room temperature. A pattern detection block scans the incoming data for patterns of sufficiently long consecutive 0's or 1's. At the end of such a pattern a valid measurement is present at the output of one of the current comparators. Based on these measurements the digital Automatic Power Control (APC) will adjust the bias (IBIAS) and modulation current (IMOD) setting of the laser driver. Tests show that the chip can stabilize and track the launched optical power with a tolerance of less than 1 dB. In these tests the pattern detection was programmed to sample the current comparators after 5 bytes (32 ns at 1.25 Gbps) of consecutive 1's and 0's. Automatic power control on such short strings of data has not been demonstrated before. Although this laser transmitter was developed for FSAN GPON applications at a speed of 1.25 Gbps upstream, the design concept is generic and can be applied for developing a wide range of burst mode laser transmitters. This chip was developed in a 0.35 µm SiGe BiCMOS process.

A novel parallel acceleration technique is proposed based on intrinsic parallelism characteristics of shooting-and-bouncing ray launching (SBR) algorithm, which has been implemented using the MPI parallel library on common PC cluster instead of dedicated parallel machines. The results reveal that the new technique achieves very large speedup gains and could be the efficient and low-cost propagation prediction solution.

A directional audible sound can be generated by amplitude-modulated (AM) into ultrasound wave from a parametric array. To synthesize audio signals produced by the self-demodulation effect of the AM sound wave, a quasi-linear analytical solution, which describes the nonlinear wave propagation, is developed for fast numerical evaluation. The radiated sound field is expressed as the superposition of Gaussian Beams. Numerical results are presented for a rectangular parametric loudspeaker, which are in good agreement with the experimental data published previously.

We propose a robust edge detection method based on independent component analysis (ICA). It is known that most of the basis functions extracted from natural images by ICA are sparse and similar to localized and oriented receptive fields, and in the proposed edge detection method, a target image is first transformed by ICA basis functions and then the edges are detected or reconstructed with sparse components only. Furthermore, by applying a shrinkage algorithm to filter out the components of noise in the ICA domain, we can readily obtain the sparse components of the original image, resulting in a kind of robust edge detection even for a noisy image with a very low SN ratio. The efficiency of the proposed method is demonstrated by experiments with some natural images.