In this letter, we present the new type parallel-coupled band-pass filter (BPF) which uses the dielectric guide in coupled sections with finite metallization thickness. A mode-matching method has been used to analyze this new structure and the simulation results are shown and validated through comparison with other available data. The results in this letter show that the dielectric guide of coupled lines with finite metal strips can be newly added to the design parameters of the parallel-coupled BPF structure and other microwave applications.

Although many researchers have verified the superiority of Support Vector Machine (SVM) on text categorization tasks, some recent papers have reported much lower performance of SVM based text categorization methods when focusing on all types of parts of speech (POS) as input words and treating large numbers of training documents. This was caused by the overfitting problem that SVM sometimes selected unsuitable support vectors for each category in the training set. To avoid the overfitting problem, we propose a two step text categorization method with a variable cascaded feature selection (VCFS) using SVM. VCFS method selects a pair of the best number of words and the best POS combination for each category at each step of the cascade. We made use of the difference of words with the highest mutual information for each category on each POS combination. Through the experiments, we confirmed the validation of VCFS method compared with other SVM based text categorization methods, since our results showed that the macro-averaged F1 measure (64.8%) of VCFS method was significantly better than any reported F1 measures, though the micro-averaged F1 measure (85.4%) of VCFS method was similar to them.

This paper describes the operation and the test results of a novel comparator, called a differential voltage (ΔV) comparator, which detects the difference between two input signal voltages. This comparator utilizes variable threshold voltage inverters (VT-INVs) which can change a logic threshold continuously using a variable channel size MOSFETs (VS-MOSs). The circuit configuration is very simple, and has the potential to achieve high integration and low power consumption in mixed signal system LSIs.

Nearly 1/f processes are known as important stochastic models for scale invariant data analysis in a number of fields. In this paper, two parameter estimation methods of nearly 1/f processes based on wavelets are proposed. The conventional method based on wavelet transform with EM algorithm does not give the reliable parameter estimation value when the data length is short. Moreover, the precise parameter value is not estimated when the spectrum gap exists in 1/f processes. First, in order to improve the accuracy of the estimation when the data length is short, a parameter estimation method based on wavelet transform with complementary sampling is proposed. Next, in order to reduce the effect of spectrum gap, a parameter estimation method based on wavelet packet with EM algorithm is proposed. Simulation results are given to verify the effectiveness of the proposed methods.

In this paper, we propose a speech coding translation scheme by transferring coding parameters between GSM half rate and G.729 coders. Compared to the conventional decode-then-encode (DTE) scheme, the proposed parameter conversions provide speech interoperability between mobile and IP networks with reducing computational complexity and coding delay. Simulation results show that the proposed methods can reduce about 30% computational load and coding delay acquired in the target encoders and achieve almost imperceptible degradation in performance.

We present a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in conventional CMOS technology. Practical application in fully-integrated QVGA-size video-picture segmentation chips is estimated to become possible at the 90 nm technology node.

The poor capability of bandwidth management on the current CATV network hinders the promotion of multi-media streaming services. This paper proposes a solution by applying stream-code partition on the S-CDMA system adopted in the DOCSIS 2.0 standard. The method makes use of the Fine Granularity Scalability source coding and offers an efficient way for uplink rate control, so that bandwidth management can be performed in an extremely flexible manner.

A new robust extended Kalman filter is proposed for the discrete-time nonlinear systems with norm-bounded parameter uncertainties. After linearization of the nonlinear systems, the uncertainties described by the energy bounded constraint can be converted into an indefinite quadratic cost function to be minimized. The solution to the minimization problem is given by the extended Kalman filter derived in a Krein space, which leads to a robust version of the extended Kalman filter. Since the resulting robust filter has the same structure as a standard extended Kalman filter, the proposed filter can be readily designed by simply including the uncertainty terms in its formulas. The results of simulations are presented to demonstrate that the proposed filter achieves the robustness against parameter variation and performs better than the standard extended Kalman filter.

This paper describes a 51.2 GOPS video recognition processor that provides a cost effective device solution for vision-based intelligent cruise control (ICC) applications. By integrating 128 4-way VLIW (Very Low Instruction Word) processing elements and operating at 100 MHz, the processor achieves to provide a computation power enough for a weather robust lane mark and vehicle detection function written in a high level programming language, to run in video rate, while at the same time it satisfies power efficiency requirements of an in-vehicle LSI. Basing on four basic parallel methods and a software environment including an optimizing compiler of an extended C language and video-based GUI tools, efficient development of real-time video recognition applications that effectively utilize the 128 processing elements are facilitated. Benchmark results show that, this processor can provide a four times better performance compared with a 2.4 GHz general purpose micro-processor.

In this paper, a fragment-processing solution in 3D graphics rendering algorithms based on fragment lists (i.e. A-buffer) for minimizing loss of image quality is described. While all fragment information should be preserved for exact hidden surface removal, this places additional strain on hardware in terms of silicon gates and clock cycles. Therefore, we propose a fragment processing technique that can effectively merge fragments in order to decrease the depth of fragment lists. It renders scenes quite accurately even in the case when three fragments intersect each other. This algorithm improves hardware acceleration without deteriorating image quality.

Faces of a person performing freely in front of the camera can be captured in a sufficient resolution for facial parts recognition by the proposed camera system enhanced with a special PTZ camera. Head region, facial parts regions such as eyes and mouth and the borders of facial parts are extracted hierarchically by being guided by the irises and nostrils preliminarily extracted from the images of PTZ camera. In order to show the effectivity of this system, we proposed a possibility to generate the borders of facial parts of the face for the facial caricaturing and to introduce eye-contacting facial images which can eye-contact bilaterally with each other on the TV conference environment.

A new approach for electronic sealed-bid auctions that preserve the privacy of losing bids is presented. It reduces the number of operations performed by the auctioneers to O(log ); previous protocols require O(N ) or O(N log ) where the number of bidders is N and that of available bidding prices is . Namely, the number of auctioneers' operations in our auction protocol is independent of the number of bidders. This feature offers strong advantages in massive auctions. We also propose a new scheme that checks the equality of two values without disclosing them. The scheme enhances our basic auction protocol, in terms of security and communication costs.

This paper proposes a test generation method using several partly compacted test plan tables for RTL data paths. Combinational modules in data paths are tested using several partly compacted test plan tables. Each partly compacted test plan table is generated from each grouped test plan set and is used to test combinational modules corresponding to the grouped test plans. The values of control signals in a partly compacted test plan table are supplied by a test controller. This paper also proposes the architecture of a test controller which can be synthesized in a reasonable amount of time, and proposes a test plan grouping method to shorten test length for data paths under a test controller area constraint. Experimental results for benchmarks show that the test lengths are shortened by 4 to 36% with -9 to 8% additional test controller area compared with the test generation method using test plans.

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

We present a new and efficient approach for extracting on-chip mutual inductances of VLSI interconnects by applying approximation formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs because the skin and proximity effects do not affect most wires. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Within geometrical constraints, the wires are of arbitrary specification. Results of a comprehensive evaluation based on the ITRS-specified global wiring structure for 2003 shows that the inductance values were extracted by using the proposed approach, and they were within several percent of the values obtained by using commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based analysis of carry-propagation-free adders using various number representations.

Given an edge-weighted graph G, the minimum maximal matching problem asks to find a minimum weight maximal matching. The problem is known to be NP-hard even if the graph is planar and unweighted. In this paper, we consider the problem in planar graphs. First, we prove a strong inapproximability for the problem in weighted planar graphs. Second, in contrast with the first result, we show that a polynomial time approximation scheme (PTAS) for the problem in unweighted planar graphs can be obtained by a divide-and-conquer method based on the planar separator theorem. For a given ε > 0, our scheme delivers in time a solution with size at most (1 + ε) times the optimal value, where n is the number of vertices in G and α is a constant number.

A novel audio watermarking based on wavelet modulation is presented. The watermark signals are constructed by M-band wavelet modulation that can increase redundancy to improve the detection performance. In order to maximize the watermarking strength within the perceptual constraints, the watermark signals synthesized from different subbands are separately masked using a frequency auditory model. CDMA technique is implemented to achieve watermarking capacity. Experimental results show that this method is very robust.

In this paper, we propose a fault-tolerance mechanism for microprocessors, which detects transient faults and recovers from them. The investigation of fault-tolerance techniques for microprocessors is driven by two issues: One regards deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is the increasing popularity of mobile platforms. Cellular telephones are currently used for applications which are critical to our financial security, such as mobile banking, mobile trading, and making airline ticket reservations. Such applications demand that computer systems work correctly. In light of this, we propose a mechanism which is based on an instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy, and evaluate our proposal using a timing simulator.

This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.