The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

This paper proposes an efficient method for design space exploration of the global optimum configuration for parameterized ASIPs. The method not only guarantees the optimum configuration, but also provides robust speedup for a wide range of processor architectures such as SoC, ASIC as well as ASIP. The optimization procedure within this method takes a two-steps approach. Firstly, design parameters are partitioned into clusters of inter-dependent parameters using parameter dependency information. Secondly, parameters are optimized for each cluster, the results of which are merged for global optimum. In such optimization, inferior configurations are extensively pruned with a detailed optimality mapping between dependent parameters. Experimental results with mediabench applications show an optimization speedup of 4.1 times faster than the previous work on average, which is significant improvement for practical use.

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

This paper proposes a test generation method using several partly compacted test plan tables for RTL data paths. Combinational modules in data paths are tested using several partly compacted test plan tables. Each partly compacted test plan table is generated from each grouped test plan set and is used to test combinational modules corresponding to the grouped test plans. The values of control signals in a partly compacted test plan table are supplied by a test controller. This paper also proposes the architecture of a test controller which can be synthesized in a reasonable amount of time, and proposes a test plan grouping method to shorten test length for data paths under a test controller area constraint. Experimental results for benchmarks show that the test lengths are shortened by 4 to 36% with -9 to 8% additional test controller area compared with the test generation method using test plans.

This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based analysis of carry-propagation-free adders using various number representations.

In this paper, a new grouping method for Group Technology using Self-Organizing Map (SOM) is proposed. The purpose of our study is to divide machines in a factory into any number of cells so that the machines in each cell can process a similar set of parts to increase productivity. A main feature of our method is to specify not only the number of the cells but also the maximum and minimum numbers of machines in a cell. Some experimental results show effectiveness of our proposed algorithm.

A high-speed 3-D camera has a future possibility of wide variety of application fields such as quick inspection of industrial components, observation of motion/destruction of a target object, and fast collision prevention. In this paper, a row-parallel position detector for a high-speed 3-D camera based on a light-section method is presented. In our row-parallel search method, the positions of activated pixels are quickly detected by a row-parallel search circuit in pixel and a row-parallel address acquisition of O(log N) cycles in N-pixel horizontal resolution. The architecture keeps high-speed position detection in high pixel resolution. We have designed and fabricated the prototype position sensor with a 12816 pixel array in 0.35 µm CMOS process. The measurement results show it achieves quick activated-position acquisition of 450 ns for "beyond-real-time" 3-D imaging and visual feedback. The high-speed position detection of the scanning sheet beam is demonstrated.

A novel hybrid numerical method, which is based on the extended spectral domain approach combined with the mode-matching method, is applied to evaluate the scattering parameter of waveguide discontinuities. The formulation procedure utilizes the biorthogonal relation in the transformation, and the Green's functions in the spectral domain are obtained easily even in the inhomogeneous lossy regions. The present method does not include the approximate perturbational scheme, and it can evaluate accurately and stably the scattering parameters of either for the thin or thick obstacles made of the wide variety of materials, the lossless dielectrics to highly conductive media, in short computation time. The physical phenomena of transmission through the lossy obstacles are investigated by numerical computations. The results are compared with FEM where FEM computations are feasible, although the FEM computations cannot cover the whole performances of the present method. The good agreement is observed in the corresponding range. The matrix size in this method is smaller than that of other methods. Therefore, the present method is numerically efficient and it would be able to apply for the integrated evaluation of a successive discontinuity. The resonant characteristics of rectangular waveguide cavity are analyzed accurately taking the conductor losses into consideration.

The paper develops the transformation rules in order to use the Stochastic Petri Net model to evaluate the performance of various task scheduling algorithms. The transformation rules are applied to DFRN scheduling algorithm to investigate its effectiveness. The performance comparison reveals that the proposed approach provides very accurate evaluation for the scheduling algorithm when the Communication to Computation Ratio value is small.

The auction is a popular way of trading. Despite of the popularity of the auction, only a small number of papers have addressed the protocol which realize the double auction. In this paper, we propose a new method of double auction which improves the algorithm of the existing double auction protocol. Our new method is based on the idea of number comparison which is realized by homomorphic encryption. The new method solves the problem of the privacy of losing bids found in the existing algorithm. The buyers and the sellers can embed a random number in their bidding information by the use of the homomorphic encryption. The players in an auction cannot get anyone else's bidding information. The new method is more efficient than the existing ones. Our new method satisfies the criteria for the auction protocol.

One-dimentional equivalent circuit model of a heterostructure InAlAs/InGaAs/InP metal-semiconductor-metal photodetector is discussed. In this photodetector, InGaAs is used as an optical absorption layer and the InAlAs is used for Schottky barrier enhanement. The measured S11 parameter deviates from equi-resistance lines on the Smith chart, indicating the equivalent circuit is different from the conventional equivalent circuit using a series resistance, a depletion region capacitance and a depletion region resistance. The difference is due to band discontinuity at the heterojunctions, and we propose a equivalent circuit taking account of the band discontinuity. The band discontinuity is expressed by parallel combination of a resistance and a capacitance. The measured S11 parameter can be fitted well with the calculated S11 parameter from the proposed equivalent circuit, and we can successfully extract the device parameters from the fitted curve.

In this letter, we propose the Low-Density Parity-Check (LDPC) coded Orthogonal Frequency Division Multiplexing (OFDM) systems to improve the error rate performance of OFDM. We also evaluate the iterative decoding performance on both an AWGN and a frequency-selective fading channels. We show that when the energy per information bit to the noise power spectral density ratio Eb/N0 is not small, the LDPC coded OFDM (LDPC-COFDM) systems have the good error rate performance with a small number of iterations. We also show that when the Eb/N0 is small, the BER of the LDPC-COFDM systems is worse than that of the Turbo coded OFDM (TCOFDM) systems, while when the Eb/N0 is not small, the BER of the LDPC-COFDM systems is better with a small number of iterations.

In this note, we present some results about parses of codes. First we present a sufficient condition of a bifix code to have the bounded indicator. Next we consider a proper parse, introduced notion. We prove that for a strongly infix code, the number of proper parses is at most three under some condition. We also prove that if a code X has a unique proper parse for each word under the same condition, then X is a strongly infix code.

We propose a dependency parsing model for head-final, variable word order languages. Based on the observation that each word has its own preference for its modifying distance and the preferred distance varies according to surrounding context of the word, we define a parsing model that can reflect the preference. The experimental result shows that the parser based on our model outperforms other parsers in terms of precision and recall rate.

This paper proposes a simulation framework suitable for holonic manufacturing systems, or HMS, based on the concept of distributed self-simulation. HMS is a distributed system that comprises autonomous and cooperative elements called holons, for the flexible and agile manufacturing. The simulation framework proposed here capitalizes on this distributed nature, where each holon functions similar to an independent simulator with self-simulation capabilities to maintain its own clock, handle events, and detect inter-holon state inconsistencies and perform rollback actions. This paper discusses the detailed architecture and design issues of such a simulator and reports on the results of a prototype.

This investigation proposes a new multiplication algorithm in the finite field GF(2m) over the polynomial basis, in which the irreducible xm +xn + 1 with gcd(m,n) = 1 generates the field GF(2m). The algorithm involves two steps--the intermediate multiplication and the modulo reduction. In the first step, the intermediate multiplication algorithm permutes a polynomial to construct the full-bit-parallel systolic intermediate multiplier. The circuit is identical of m2 cells, each cell is identical of one 2-input AND gate, one 2-input XOR gate, and four 1-bit latches. In the second step, based on the results of the intermediate multiplication in the first step, the modulo reduction circuit is built using regular and simple reduction operations. The latency of the proposed multiplier requires m + k + 1 clock cycles, where k = + 1. Notably, the latency can be very low if n is in the range 1 n . For the computing multiplication in GF(2m), the novel multiplier exhibits much lower latency than the existing systolic multipliers, and is well suited to VLSI systems due to their regular interconnection pattern, modular structure and fully inherent parallelism.

Files of 3D mesh models are often large and hence time-consuming to retrieve from a storage device or to download through the network. Most 3D viewing applications need to obtain the entire file of a 3D model in order to display the model, even when the user is interested only in a small part, or a low-resolution version, of the model. Therefore, coding that enables multiresolution and ROI (Region Of Interest) transmission of 3D models is desired. In this paper, we propose a coding algorithm of 3D models based on partitioning schemes. The algorithm actually partitions the 3D meshes into some small sub-meshes according to some geometric criteria (such as curvatures), and then codes each small sub-meshes separately to transmit it progressively to users on demand. The key idea of this paper lies in the mesh partitioning procedure prior to its LOD control, which enables good compression ratio of the mesh data as well as some other good capable properties through network transmission such as ROI coding, view-adaptive transmission, error resilient coding, etc.

Parameter-optimized cubic convolution is used to accurately analyze the pitch center, rate and extent of vibrato tones. We interpolate the time-tracing fundamental frequencies of vibrato tones using parametric cubic convolution, and analytically estimate the positions and values of the extrema, which are used to analyze the characteristics of the vibrato. The optimal values of α, the parameter of the interpolation kernel, are also shown as a function of the normalized vibrato rates.

Space-time transmit diversity (STTD) and space-time block coding (STBC) are attractive techniques for high bit-rate and high capacity transmission. The concatenation scheme of turbo codes and STBC (Turbo-STBC) was proposed and it has been shown that the Turbo-STBC can achieve the good error rate performance. Recently, low-density parity-check (LDPC) codes have attracted much attention as the good error correcting codes achieving the near Shannon limit performance like turbo codes. The decoding algorithm of LDPC codes has less complexity than that of turbo codes. Furthermore, when the block length is large, the error rate performance of the LDPC codes is better than that of the turbo codes with almost identical code rate and block length. In this letter, we propose a concatenation scheme of LDPC codes and STBC. We refer to it as the LDPC-STBC. We evaluate the error rate performance of the LDPC-STBC by the computer simulation and show that the error rate performance of the LDPC-STBC is almost identical to or better than that of the Turbo-STBC in a flat Rayleigh fading channel.

This paper assesses the media synchronization quality of recovery control schemes from asynchrony, which are referred to as reactive control schemes here, in terms of objective and subjective measures. We deal with four reactive control techniques: skipping, discarding, shortening and extension of output duration, and virtual-time contraction and expansion. We have carried out subjective and objective assessment of the media synchronization quality of nine schemes which consist of combinations of the four techniques. The paper makes a comparison of media synchronization quality among the schemes. It also clarifies the relations between the two kinds of quality measures.