The first important step in pre-processing data for 3D virtual colonoscopy requires careful segmentation of a complicated shaped colon. We describe an automatic colon segmentation method with a new patient-friendly bowel preparation scheme. This new bowel preparation makes the segmentation more appropriate for digitally removing undesirable remains in the colon. With the aim of segmenting the colon accurately, we propose two techniques which can solve the partial-volume-effect (PVE) problem on the boundaries between low and high intensity regions. Based on the features of the adverse PVE voxels on the gas and fluid boundary inside the colon, our vertical filter eliminates these PVE voxels. By seriously considering the PVE on the colon boundary, our gradient-magnitude-based region growing algorithm improves the accuracy of the boundary. The result of the automatic colon segmentation method is illustrated with both extracted 2D images from the experimental volumetric abdominal CT datasets and a reconstructed 3D colon model.

As one form of electronic commerce, the scale of online trading in stocks is rapidly growing. Although brokers lie between the customers as trustees in the current market, retrenchment of broker seems inevitable. This paper proposes a protocol that allows trading to proceed with only the market and the customers. We show the required characteristics for this type of trading at first. Next, to fulfil these characteristics, we apply an electronic auction protocol and digital signatures. The result is a trading protocol with security equivalent to that the current trading system.

In this paper, we attempt to construct practical secret sharing schemes, which scheme has smaller share size and can detect cheating with high probability. We define two secure ramp schemes, secure ramp scheme and strongly secure ramp scheme. Then, we propose two constructions of secure ramp scheme. These schemes both have small share size and the cheating can be detected with high probability. So, they are practical secret sharing schemes.

This paper presents a new effective partitioning technique of linearly transformed input space in Adaptive Network based Fuzzy Inference System (ANFIS). The ANFIS is the fuzzy system with a hybrid parameter learning method, which is composed of a gradient and a least square method. The input space can be partitioned flexibly using new modeling inputs, which are the weighted linear combination of the original inputs by the proposed input partitioning technique, thus, the parameter learning time and the modeling error of ANFIS can be reduced. The simulation result illustrates the effectiveness of the proposed technique.

In this paper, we present a computer-aided diagnosis (CAD) system to automatically detect lung cancer candidates at an early stage using a present and a past helical CT screening. We have developed a slice matching algorithm that can automatically match the slice images of a past CT scan to those of a present CT scan in order to detect changes in the lung fields over time. The slice matching algorithm consists of two main process: the process of extraction of the lungs, heart, and descending aorta and the process of matching slices of the present and past CT images using the information of the lungs, heart, and descending aorta. To evaluate the performance of this algorithm, we applied it to 50 subjects (total of 150 scans) screened between 1993 and 1998. From these scans, we selected 100 pairs for evaluation (each pair consisted of scans for the same subject). The algorithm correctly matched 88 out of the 100 pairs. The slice images for the present and past CT scans are displayed in parallel on the CRT monitor. Feature measurements of the suspicious regions are shown on the relevant images to facilitate identification of changes in size, shape, and intensity. The experimental results indicate that the CAD system can be effectively used in clinical practice to increase the speed and accuracy of routine diagnosis.

A uniquely parsable unification grammar (UPUG) is a formal grammar with the following features: (1) parsing is performed without backtracking, and (2) each nonterminal symbol can have arguments, and derivation and parsing processes accompany unification of terms as in Prolog (or logic programming). We newly introduce a uniquely parallel parsable unification grammar (UPPUG) by extending the framework of a UPUG so that parallel parsing is also possible. We show that, in UPPUG, parsing can be done without backtracking in both cases of parallel and sequential reductions. We give examples of UPPUGs where a given input string can be parsed in sublinear number of steps of the length of the input by parallel reduction.

A high Tc superconducting quantum interference device (SQUID) magnetometer system is developed for the application to biological immunoassay. In this application, magnetic nanoparticles are used as magnetic markers to perform immunoassay, i.e., to detect binding reaction between an antigen and its antibody. The antibody is labeled with γ-Fe2O3 nanoparticles, and the binding reaction can be magnetically detected by measuring the magnetic field from the nanoparticles. Design and set up of the system is described, and the sensitivity of the system is studied in terms of detectable number of the magnetic markers. At present, we can detect 4106 markers when the diameter of the marker is 50 nm. Total weight of the magnetic nanoparticles becomes 520 pg in this case. An experiment is also conducted to measure antigen-antibody reaction with the present system. It is shown that the sensitivity of the present system is 10 times better than that of the conventional method using an optical marker. A one order of magnitude improvement of sensitivity will be realized by the sophistication of the present system.

We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.

We propose a blind source separation algorithm for the mixture of finite alphabet sources where sensors are less than sources. The algorithm consists of an update equation of an estimated mixing matrix and enumeration of the inferred sources. We present the bound of a step size for the stability of the algorithm and two methods of assignment of the initial point of the estimated mixing matrix. Simulation results verify the proposed algorithm.

This paper treats meta-heuristics for combinatorial optimization problems. The parallelization of meta-heuristics is then discussed in which we show that parallel processing has possibility of not only speeding up but also improving solution quality. Finally we extend the discussion of the combinatorial optimization into autonomous decentralized systems, say autonomous decentralized optimization. This notion becomes very important with the advancement of the network-connected system architecture.

We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.

To extract extrinsic resistances, conventional cold-FET methods require additional DC measurements or channel technological parameters. Additionally, the methods need at least two sets of cold-FET S-parameters measured at different cold-FET bias conditions in order to completely determine gate and drain pad capacitance as well as extrinsic gate, source and drain inductance and their resistances. One set of S-parameters handles the extraction of extrinsic inductances, and the other set extracts the gate and drain pad capacitance. To be free from additional DC measurement or channel technological parameters and reduce the number of sets of cold-FET S-parameters, we propose a cold-FET method that can extract all the extrinsic elements including the gate and drain capacitance, using only one set of cold-FET S-parameters. The method has shown excellent agreement between modeled and measured S-parameters up to 62 GHz at 56 different normal operating bias points.

Nonlinear characteristics of a DBR (Distributed Bragg Reflector) Cherenkov laser are investigated with the aid of particle simulation, allowing for the nonlinear properties of the electron beam. Numerical results show that the EM power extracted from the cavity is considerably suppressed by the nonlinear effect of the electron beam. Additionally, the extracted EM power is found to be critically dependent on the reflection coefficient of the DBR at the output end. Thus the DBRs at both ends of the cavity should be carefully designed in order to extract the EM power from the cavity efficiently.

Superscalar processors can achieve increased performance by issuing instructions Out-of-Order (OoO) from the original instruction stream. Implementing an OoO instruction scheme requires a hardware mechanism to prevent incorrectly executed instructions from updating registers values. In addition, performance decreases if data dependencies, a branch or a trap among instructions appears. To this end we propose a new mechanism named Dynamic Fast Issue (DFI) mechanism to issue instructions in an OoO fashion to multiple parallel functional units without considerable hardware complexity. The above system, which will be implemented in our Superscalar Functional Assignments Register Microprocessor(FARM), solves data dependencies, supports precise interrupt and branch prediction, which are the main problems associated with the dynamic scheduling of instructions in superscalar machines. Results are written only once,Write-once, directly into the register file (RF). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a status buffer (STB). A 64 entries integrated register file is implemented to hold both renamed and logical registers. To recover the processor state from an interrupt or a branch miss-prediction, a status buffer (STB) and a recovery list table (RLT) are implemented. Novel aspects of the above system architecture as well as the principle underlying this process and the constraints that must be met is presented. Performance evaluation results are performed through full-pipelined-level architectural simulator and SPECint95 benchmark programs.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

A simple but effective fundamental frequency estimation method is proposed using parametric cubic convolution. The performance of the method is shown to be good not only for the stationary signals but also for the signal whose fundamental frequency is changing with time. In the simulation, comparisons with other high-accuracy methods are also shown. Due to its accuracy and simplicity, the proposed method is practically useful.

This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

This paper describes a new algorithm for configuring the array of adders used to add the partial products in a multiplier circuit. The new algorithm reduces not only the number of half adders in an adder tree, but also the number of operands passed to the block generating the final product in a multiplier. The arrays obtained with this algorithm are smaller than Wallace's ones and have fewer outputs than Dadda's arrays. We show some evaluation figures and preliminary simulation results of 4, 8 and 16-bit tree configurations.

This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

This paper introduces a flexible, stream-oriented dataflow processing model based on the "Communicating Logic (CL)" framework. As the target architecture, we adopt the dual layered "Plastic Cell Architecture (PCA). " Datapath processing functionality is encapsulated in asynchronous hardware objects with variable graining and implemented using look-up tables. Communication (i.e. connectivity and control) between the distributed processing objects is achieved by means of inter-object message passing. The key point of the CL approach is that it offers the merits of scalable performance, low power hardware implementation with the user friendly compilation and linking capabilities unique to software.