This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.

We give an overview of the computational complexity of linear and mesh-connected cellular and iterative arrays with respect to well known models of sequential and parallel computation. We discuss one-way communication versus two-way communication, serial input versus parallel input, and space-efficient simulations. In particular, we look at the parallel complexity of cellular arrays in terms of the PRAM theory and its implications, e.g., to the parallel complexity of recurrence equations and loops. We also point out some important and fundamental open problems that remain unresolved. Next, we investigate the solvability of some reachability and safety problems concerning machines operating in parallel and cite some possible applications. Finally, we briefly discuss the complexity of the "commutativity analysis" technique that is used in the areas of parallel computing and parallelizing compilers.

A method of learning for multi-layer artificial neural networks is proposed. The learning model is designed to provide an effective means of escape from the Backpropagation local minima. The system is shown to escape from the Backpropagation local minima and be of much faster convergence than simulated annealing techniques by simulations on the exclusive-or problem and the Arabic numerals recognition problem.

In this paper, we propose an activity-based estimation scheme to determine the received signal power disparity, that enhances the BER performance of the SIC scheme in a DS/CDMA system considering a practical voice activity factor, and compare BER performance with those of other schemes with or without estimation. Numerical analysis results show that the SIC scheme with the proposed activity-based estimation improves the BER performance compared with that without considering voice activity, and it approaches to that of the ideal estimation as the total number of concurrent users increases. In addition, the higher becomes the maximum attainable SNR, the better becomes the BER performance of the proposed activity-based estimation scheme.

This paper develops a simple algorithm for calculating a polynomial curve or surface in a parallel way. The number of arithmetic operations and the necessary time for the calculation are evaluated in terms of polynomial degree and resolution of a curve and the number of processors used. We made some comparisons between our method and a conventional method for generating polynomial curves and surfaces, especially in computation time and approximation error due to the reduction of the polynomial degree. It is shown that our method can perform fast calculation within tolerable error.

A near-optimum parallel algorithm for bipartite subgraph problem using gradient ascent learning algorithm of the Hopfield neural networks is presented. This parallel algorithm, uses the Hopfield neural network updating to get a near-maximum bipartite subgraph and then performs gradient ascent learning on the Hopfield network to help the network escape from the state of the near-maximum bipartite subgraph until the state of the maximum bipartite subgraph or better one is obtained. A large number of instances have been simulated to verify the proposed algorithm, with the simulation result showing that our algorithm finds the solution quality is superior to that of best existing parallel algorithm. We also test the proposed algorithm on maximum cut problem. The simulation results also show the effectiveness of this algorithm.

Low-crosstalk 1.3-µm Fabry-Perot laser diode (FP-LD) and photodiode (PD) arrays are developed. The arrays are fabricated on semi-insulating substrates and their anodes and cathodes are separated channel by channel to suppress inter-channel electrical crosstalk at high frequency. Crosstalk of less than -30 dB is achieved between neighboring LDs at 3.125 GHz. This is low enough for BER characteristics observed under asynchronous operation of a 4-channel LD array to be no worse than those under single-channel operation. Excellent uniformity of both LD and PD characteristics, high-temperature operation of the LD array, and low-voltage operation of the PD array are also attained. These arrays are suitable for low-cost high-bit-rate parallel optical communications.

OFDM modulation has attracted attention for fourth-generation mobile communication systems and high-speed wireless LANs. However, it has a very serious problem of large peak power. PTS (partial transmit sequences) has been proposed as one solution to this problem. In PTS, the OFDM subcarriers are divided into several clusters, and the phase of each cluster is rotated by a complex weight to minimize the PAPR (peak-to-average power ratio). However, the weight of the phase rotation must be sent to the mobile terminal by using a side information channel. In this paper, we propose two weight estimation methods at the receiver to avoid weight transmission in side information channels. The first method uses pilot signals, while the second is a blind estimation method that changes the weight pattern. We evaluate the performance of these methods by computer simulation.

In this paper, we propose a novel electronic bearer check system (EBC). This system allows the consumer to pay any amount of money below an upper-boundary on the Internet within an expiration period. During each transaction, the consumer does not need to contact the bank's server. Furthermore, this electronic bearer check can be transferred to any third party. The off-line characteristic of our system is very convenient for the consumer. Moreover, the double spending and double depositing problem will not occur in this system. More importantly, the framework of this system provides anonymity to protect customer privacy.

In a shared buffer packet switch, a good buffer management scheme is needed to reduce the overall packet loss probability and improve the fairness between different users. In this paper, a novel buffer control scheme called partial sharing and partial partitioning (PSPP) is proposed. The PSPP is an adaptive scheme that can be dynamically adjusted to the changing traffic conditions while simple to implement. The key idea of the PSPP is that part of the buffer space, proportional to the number of inactive output ports, is reserved for sharing between inactive output ports. This portion of buffer is called PS buffer. The residual buffer space, called PP buffer, is partitioned and distributed to active output ports equally. From the analysis results, we only need to reserve a small amount of PS buffer space to get good performance for the entire system. Computer simulation shows the PSPP control is very robust and very close to the performance of pushout (PO) buffer management scheme which is a scheme considered as optimal in terms of fairness and total loss ratio while too complicated for implementation.

Several gateway-based congestion control mechanisms have been proposed to support an end-to-end congestion control mechanism of TCP (Transmission Control Protocol). One of promising gateway-based congestion control mechanisms is a RED (Random Early Detection) gateway. Although effectiveness of the RED gateway is fully dependent on a choice of control parameters, it has not been fully investigated how to configure its control parameters. In this paper, we analyze the steady state behavior of the RED gateway by explicitly modeling the congestion control mechanism of TCP. We first derive the equilibrium values of the TCP window size and the buffer occupancy of the RED gateway. Also derived are the stability condition and the transient performance index of the network using a control theoretic approach. Numerical examples as well as simulation results are presented to clearly show relations between control parameters and the steady state behavior.

We propose a new and fast full search (FS) motion estimation algorithm for video coding. The computational reduction comes from sequential rejection of impossible candidates with derived formula and subblock norms. Our algorithm reduces more the computations than the recent fast full search (FS) motion estimation algorithms.

We have developed optical encoding devices for processing femtosecond pulses. These devices are based on spectral separation devices and light modulators with fiber gratings. Experiments were made to encode a light pulse in the spectral domain. These experiments utilize the characteristics that a femtosecond light pulse has a very broad spectrum. An input femtosecond light pulse is decomposed into a series of wavelength components. Each wavelength component with narrow spectra <1 nm width is successfully extracted into a single mode fiber. Light modulators corresponding to wavelength components are assigned to the 1st bit, the 2nd bit, the 3rd bit, , the nth bit, respectively. All of the encoded wavelength components are again recombined into a single time-varying signal and transmitted through an optical fiber. Decoding at receiving site is made by the reverse operation. Encoding and decoding for 2-bit and 4-bit signals were demonstrated for 200 fs input light pulse with about 40 nm spectral width.

Deterministic execution testing has been considered a promising way for concurrent program testing because of its ability to replay a program's execution. Since, however, deterministic execution requires that a synchronization event sequence to be replayed be feasible and valid, it is not directly applicable to a situation in which synchronization sequences, being valid but infeasible, are taken into account. Resolving this problem is very important because a program may still meet its specification although the feasibility of all valid sequences is not satisfied. In this paper, we present a new approach to deterministic execution for testing concurrent systems. The proposed approach makes use of the notion of event independence and constructs an automation which accepts all the sequences semantically equivalent to a given event sequence to be replayed. Consequently, we can allow a program to be executed according to event sequences other than the given (possible infeasible) sequence if they can be accepted by the automation.

This letter describes a new parallel combinatorial delayed multiplexing CDMA system for high-bit-rates mobile communications. It combines delayed multiplexing and parallel combinatory methods with the CDMA system to provide higher bit rates without the use of complex receivers. The results of computer simulations using the double-spike Rayleigh fading channel model in a multiple-user environment show that its down-link BER performance is the same as that of the conventional multicode system.

This paper investigates the interference suppression effect from much higher rate dedicated physical channels (DPCHs) of a parallel-type coherent multistage interference canceller (COMSIC) with iterative channel estimation (ICE) by laboratory experiments in the transmit-power-controlled W-CDMA reverse link. The experimental results elucidate that when two interfering DPCHs exist with the spreading factor (SF) of 8 and with the ratio of the target signal energy per bit-to-interference power spectrum density ratio (Eb/I0) of fast transmit power control, ΔEb/I0, of -6 dB (which corresponds to 64 simultaneous DPCHs with SF = 64, i.e., the same symbol rate as the desired DPCH), the implemented COMSIC receiver with ICE exhibits a significant decrease in the required transmit signal energy per bit-to-background noise power spectrum density ratio (Eb/N0) at the average bit error rate (BER) of 10-3 (while the matched filter (MF)-based Rake receiver could not realize the average BER of 10-3 due to severe multiple access interference (MAI)). It is also found that the achieved BER performance at the average BER of 10-3 of the COMSIC receiver with the A/D converter quantization of 8 bits in the laboratory experiments is degraded by approximately 1.0 dB and 4.0 dB compared to the computer simulation results, when ΔEb/I0=-6 dB and -9 dB, respectively, due to the quantization error of the desired signal and path search error for the Rake combiner. Finally, we show that the required transmit Eb/N0 at the average BER of 10-3 of the third-stage COMSIC with ICE is decreased by approximately 0.3 and 0.5 dB compared to that of COMSIC with decision-feedback type channel estimation (DFCE) with and without antenna diversity reception, respectively.

Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

This paper introduces fast methods for variable length decoding (VLD) and inverse quantization (IQ) on software MPEG-2 decoders by using Single Instruction stream Multiple Data stream (SIMD) type instructions for multimedia applications. With the VLD implementation, the VLD tables are made as small as possible so as to minimize missed cache accesses, and variable length codewords are decoded concurrently. With the IQ implementation, inverse quantization of the VLD results is performed in parallel. When these methods are used, combined clock cycles for VLD and IQ are roughly 30% shorter than those resulting from conventional methods, and this effect is especially pronounced for high bitrate streams.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.

In this paper, a discrete-time convergence theorem for continuous-state Hopfield networks with self-interaction neurons is proposed. This theorem differs from the previous work by Wang in that the original updating rule is maintained while the network is still guaranteed to monotonically decrease to a stable state. The relationship between the parameters in a typical class of energy functions is also investigated, and consequently a "guided trial-and-error" technique is proposed to determine the parameter values. The third problem discussed in this paper is the post-processing of outputs, which turns out to be rather important even though it never attracts enough attention. The effectiveness of all the theorems and post-processing methods proposed in this paper is demonstrated by a large number of computer simulations on the assignment problem and the N-queen problem of different sizes.