This paper deals with a design problem of a robust controller which achieves not only robust stability but also a performance robustness for linear systems with structured uncertainties satisfying matching condition. The performance robustness means that comparing the transient behavior of the uncertain system with a desired one generated by the nominal system, the deterioration of control performance is suppressed. In this approach, the control law consists of a state feedback with the fixed gain designed by using the nominal system, a state feedback with an adaptive gain determined by a parameter adjustment law and a compensation input for the purpose of keeping transient behavior as closely as possible to the desirable one. We show the parameter adjustment law in order to guarantee robust stability and that the condition for the existence of the compensation input is equivalent to the Riccati equation for the standard linear quadratic control problem. Finally, numerical examples are presented.

The equidistortion principle[1] has recently been proposed as a basic principle for design of an optimal vector quantization (VQ) codebook. The equidistortion principle adjusts all codebook vectors such that they have the same contribution to quantization error. This paper introduces a novel VQ codebook design algorithm based on the equidistortion principle. The proposed algorithm is a variant of the law-of-the-jungle algorithm (LOJ), which duplicates useful codebook vectors and removes useless vectors. Due to the LOJ mechanism, the proposed algorithm can establish the equidistortion condition without wasting learning steps. This is significantly effective in preventing performance degradation caused when initial states of codebook vectors are improper to find an optimal codebook. Therefore, even in the case of improper initialization, the proposed algorithm can achieve minimization of quantization error based on the equidistortion principle. Performance of the proposed algorithm is discussed through experimental results.

In this paper, we propose an algorithm that automatically generates the intermediate scenes using the bidirectional disparity morphing (BDM) from the parallel stereo images. The two-step search strategy is used for speeding up the computation of the bidirectional disparity map and three occluding patterns are used for smoothing the computed disparities more elaborately. Using the bidirectional disparity map, we interpolate the left and the right image to their intermediate scenes. Then we dissolve two interpolated images into the desired intermediate scene which the holes are removed and the effect of the disparity estimation errors is minimized. We implemented the proposed algorithm on TM1300 supported by TriMedia using pSOSytem which enables to do multiprocessing. As a result, we can interpolate the high-quality intermediate scenes with real-time process.

Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

Assume that each edge e of a graph G is assigned a list (set) L(e) of colors. Then an edge-coloring of G is called an L-edge-coloring if each edge e of G is colored with a color contained in L(e). In this paper, we prove that any series-parallel simple graph G has an L-edge-coloring if |L(e)| max{3,d(v),d(w)} for each edge e = vw, where d(v) and d(w) are the degrees of the ends v and w of e, respectively. Our proof yields a linear algorithm for finding an L-edge-coloring of series-parallel graphs.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.

The main contribution of this paper is to present an FPGA-based implementation of an instance-specific hardware which accelerates the CKY (Cocke-Kasami-Younger) parsing for context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines whether G derives x. We have developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any given context-free grammar G. The generated source is embedded in an FPGA using the design software provided by the FPGA vendor. We evaluated the instance-specific hardware, generated by our hardware generator, using a timing analyzer and tested it using the Altera FPGAs. The generated hardware attains a speed-up factor of approximately 750 over the software CKY parsing algorithm.

This paper describes multigrain parallel processing on OSCAR (Optimally SCheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for overlapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3.84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.

A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.

A heterogeneous parallel computing environment consisting of different types of workstations and communication links plays an important role in parallel computing. In many applications on the system, collective communication operations are commonly used as communication primitives. Thus, design of the efficient collective communication operations is the key to achieve high-performance parallel computing. But the heterogeneity of the system complicates the design. In this paper, we consider design of an efficient gather operation, one of the most important collective operations. We show that an optimal gather schedule is found in O(n2k-1) time for the heterogeneous parallel computing environment with n processors of k distinct types, and that a nearly-optimal schedule is found in O(n) time if k=2.

We propose a new algorithm for blind source separation (BSS), in which frequency-domain independent component analysis (FDICA) and time-domain ICA (TDICA) are combined to achieve a superior source-separation performance under reverberant conditions. Generally speaking, conventional TDICA fails to separate source signals under heavily reverberant conditions because of the low convergence in the iterative learning of the inverse of the mixing system. On the other hand, the separation performance of conventional FDICA also degrades significantly because the independence assumption of narrow-band signals collapses when the number of subbands increases. In the proposed method, the separated signals of FDICA are regarded as the input signals for TDICA, and we can remove the residual crosstalk components of FDICA by using TDICA. The experimental results obtained under the reverberant condition reveal that the separation performance of the proposed method is superior to those of TDICA- and FDICA-based BSS methods.

This paper proposes a gesture recognition method which uses higher order local autocorrelation (HLAC) features extracted from PARCOR images. To extract dominant information from a sequence of images, we apply linear prediction coding technique to the sequence of pixel intensities and PARCOR images are constructed from the PARCOR coefficients of the sequences of the pixel values. From the PARCOR images, HLAC features are extracted and the sequences of the features are used as the input vectors of the Hidden Markov Model (HMM) based recognizer. Since HLAC features are inherently shift-invariant and computationally inexpensive, the proposed method becomes robust to changes in the person's position and makes real-time gesture recognition possible. Experimental results of gesture recognition are shown to evaluate the performance of the proposed method.

With the aim of enabling concatenative synthesis of expressive speech, we herein report progress towards developing robust and automatic algorithms for paralinguistic annotation of very large recorded-speech corpora. In particular, we describe a method of combining robust acoustic-prosodic and cepstral analyses to locate centres of acoustic-phonetic reliability in the speech stream, wherein physiologically meaningful parameters related to voice quality can be estimated more reliably. We then report some evaluations of a specific voice-quality parameter known as the glottal Amplitude Quotient (AQ), which was proposed in [2],[6] and is here measured automatically at centres of reliability in continuous speech. Analyses of a large, single-speaker corpus of emotional speech first validate the perceptual importance of the AQ parameter in quantifying the mode of phonation along the pressed-modal-breathy continuum, then reveal some of its phonetic, prosodic, and paralinguistic dependencies.

In this paper we consider blind source separation (BSS) problem of signals which are spatially uncorrelated of order four, but temporally correlated of order four (for instance speech or biomedical signals). For such type of signals we propose a new sufficient condition for separation using fourth order statistics, stating that the separation is possible, if the source signals have distinct normalized cumulant functions (depending on time delay). Using this condition we show that the BSS problem can be converted to a symmetric eigenvalue problem of a generalized cumulant matrix Z(4)(b) depending on L-dimensional parameter b, if this matrix has distinct eigenvalues. We prove that the set of parameters b which produce Z(4)(b) with distinct eigenvalues form an open subset of RL, whose complement has a measure zero. We propose a new separating algorithm which uses Jacobi's method for joint diagonalization of cumulant matrices depending on time delay. We empasize the following two features of this algorithm: 1) The optimal number of matrices for joint diago- nalization is 100-150 (established experimentally), which for large dimensional problems is much smaller than those of JADE; 2) It works well even if the signals from the above class are, additionally, white (of order two) with zero kurtosis (as shown by an example).

For any pair of distinct nodes in an n-pancake graph, we give an algorithm for construction of n-1 internally disjoint paths connecting the nodes in the time complexity of polynomial order of n. The length of each path obtained and the time complexity of the algorithm are estimated theoretically and verified by computer simulation.

In this paper, a novel confidence scoring method that is applied to N-best hypotheses (word candidates) output from an HMM-based classifier is proposed. In the first pass of the proposed method, the HMM-based classifier with monophone models outputs N-best hypotheses and boundaries of all monophones in the hypotheses. In the second pass, an SM (Subspace Method)-based verifier tests the hypotheses by comparing confidence scores. To test the hypotheses, at first, the SM-based verifier calculates the similarity between phone vectors and an eigen vector set of monophones, then this similarity score is converted into a likelihood score with normalization of acoustic quality, and finally, an HMM-based likelihood of word level and an SM-based likelihood of monophone level are combined to formulate the confidence measure. Two kinds of experiments were performed to evaluate this confidence measure on speaker-independent word recognition. The results showed that the proposed confidence scoring method significantly reduced the word error rate from 4.7% obtained by the standard HMM classifier to 2.0%, and in an unknown word rejection, it reduced the equal error rate from 9.0% to 6.5%.

It is well known that KT method proposed by R. Kumaresan and D. W. Tufts is used as a popular parameter estimation method of exponentially damped signal. It is based on linear backward-prediction method and singular value decomposition (SVD). However, it is difficult to estimate parameters correctly by KT method in the case when high noise exists in the signal. In this paper, we propose a parameter (frequency components and damping factors) estimation method to improve the performance of KT method under high noise. In our proposed method, we find the signal zero groups by calculating zeros with different data record lengths according to the combination of forward-prediction and backward-prediction, the mean value of the zeros in the signal zero groups are calculated to estimate the parameters of the signal. The proposed method can estimate parameters correctly and accurately even when high noise exists in the signal. Simulation results are shown to confirm the effectiveness of the proposed method.

Based on a Quantum-inspired Evolutionary Algorithm (QEA), a new disk allocation method is proposed for distributing buckets of a binary cartesian product file among unrestricted number of disks to maximize concurrent disk I/O. It manages the probability distribution matrix to represent the qualities of the genes. Determining the excellent genes quickly makes the proposed method have faster convergence than DAGA. It gives better solutions and 3.2 - 11.3 times faster convergence than DAGA.

The problem of separating blindly independent sources from a convolutive mixture cannot be addressed in its widest generality without resorting to statistics of order higher than two. The core of the problem is in fact to identify the paraunitary part of the mixture, which is addressed in this paper. With this goal, a family of statistical contrast is first defined. Then it is shown that the problem reduces to a Partial Approximate Joint Diagonalization (PAJOD) of several cumulant matrices. Then, a numerical algorithm is devised, which works block-wise, and sweeps all the output pairs. Computer simulations show the good behavior of the algorithm in terms of Symbol Error Rates, even on very short data blocks.

As a typical planar antenna in Japan, a microstrip antenna and radial line slot antenna are chosen and some original technologies are introduced for them. About the microstrip antenna, the analyzing method is described first and the method based on the theory of microstrip planar circuit born in Japan is introduced. According to the formulas derived by this method, the design procedure considering the bandwidth is established. In addition, it is shown clearly that a microstrip antenna can produce the circular polarizations at two kinds of frequencies with a single feed. Furthermore, two kinds of broadband techniques born in Japan are picked up. About other unique microstrip antennas, they may be introduced in a suitable section each time. As for the RLSA, the history on invention is briefly presented. The radiation mechanisms depending on the slot-set arrangement and the excitation mode are discussed. The slot-coupling analysis to simulate the excitation of a two-dimensional uniformly-excited slot array is explained. The simple design based on the operation with traveling-wave propagation is also described. The technical progress to keep high efficiency in a wide gain range for satellite-TV reception is reviewed. Extensions of the RLSAs to millimeter-wave bands and plasma etching systems are finally summarized.