Clocked cascade voltage switch logic (C2VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C2VSL circuits, SET effects on C2VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C2VSL have increased tolerance to SET.

As the demand for spectrum for future wireless communication services increases, cognitive radio technology has been developed for dynamic and opportunistic spectrum access, which enables the secondary users to use the underutilized licensed spectrum of the primary users. In particular, the recent studies on the MAC protocol for dynamic and opportunistic access have focused on sensing and using the vacant spectrum efficiently. Under the ad-hoc network environment, how the secondary users use the unused channels by the primary users affects the efficient utilization of channels and a cognitive radio system is required to follow the rapid and frequent changes in channel status. In this paper, we propose a self-scheduling multi-channel cognitive MAC (SMC-MAC) protocol, which allows multiple secondary users to transmit data though the sensed idle channels by two cooperative channel sensing algorithms, i.e., fixed channel sensing (FCS) and adaptive channel sensing (ACS), and by slotted contention mechanism to exchange channel request information for self-scheduling. The performance of the proposed SMC-MAC protocol is investigated via analysis and simulations. According to the results, the proposed SMC-MAC protocol is effective in allowing multiple secondary users to transmit data frames effectively on multi-channels and adaptively in response to the primary users' traffic dynamics.

In optical packet switches, the overhead of reconfiguring a switch fabric is not negligible with respect to the packet transmission time and can adversely affect switch performance. The overhead increases the average waiting time of packets and worsens throughput performance. Therefore, scheduling packets requires additional considerations on the reconfiguration frequency. This work intends to analytically find the optimal reconfiguration frequency that minimizes the average waiting time of packets. It proposes an analytical model to facilitate our analysis on reconfiguration optimization for input-buffered optical packet switches with the reconfiguration overhead. The analytical model is based on a Markovian analysis and is used to study the effects of various network parameters on the average waiting time of packets. Of particular interest is the derivation of closed-form equations that quantify the effects of the reconfiguration frequency on the average waiting time of packets. Quantitative examples are given to show that properly balancing the reconfiguration frequency can significantly reduce the average waiting time of packets. In the case of heavy traffic, the basic round-robin scheduling scheme with the optimal reconfiguration frequency can achieve as much as 30% reduction in the average waiting time of packets, when compared with the basic round-robin scheduling scheme with a fixed reconfiguration frequency.

In this paper, we propose a simple but effective way of improving the performance of channel estimation (CE) for pilot cyclic prefixed single carrier (PCP-SC) system. The proposed method utilizes the property that the shifting signal of the PCP pilot signal can also be utilized to estimate the channel information. The receiver can continuously estimate the channel information by just shifting the received pilot signal. Regardless of the signal-to-noise ratio (SNR) and the pilot type, the proposed method can achieve about a 1.72 dB performance gain in terms of the mean squared error (MSE) of channel estimation with a slight increase in computational complexity. The BER performance with the proposed CE improvement are evaluated in a multipath fading channel using a zero-forcing (ZF) equalizer and an minmum mean squared error (MMSE) equalizer by computer simulation. It is shown that the proposed CE improvment method using an MMSE equalizer which has an unbiased vlaue of noise variance (NV) estimator gives a promising BER performance. The proposed method also benefits the estimation of the SNR for the single carrier system.

This letter is devoted to derivation of a transformation law which converts a class of nonlinear affine control systems with n-states and 2-iputs into simpler systems with chained structure. First, we give a problem formulation that we consider throughout this letter. We next introduce a transformation law and gives its mathematical certification. Then, we apply the transformation method to an example and consider control design based on chained structure for the example in order to confirm the effectiveness of our approach.

The least-squares probabilistic classifier (LSPC) is a computationally-efficient alternative to kernel logistic regression. However, to assure its learned probabilities to be non-negative, LSPC involves a post-processing step of rounding up negative parameters to zero, which can unexpectedly influence classification performance. In order to mitigate this problem, we propose a simple alternative scheme that directly rounds up the classifier's negative outputs, not negative parameters. Through extensive experiments including real-world image classification and audio tagging tasks, we demonstrate that the proposed modification significantly improves classification accuracy, while the computational advantage of the original LSPC remains unchanged.

In this paper, a differential input/output linear MOS transconductor using an adaptively biasing technique is proposed. The proposed transconductor based on a differential pair is linearized by employing an adaptively biasing circuit. The linear characteristic of the individual differential output currents are obtained by introducing the adaptively biased currents to terminate the differential output terminals. Using the proposed technique, the common-mode rejection ration (CMRR) becomes high. Simulation results show that the proposed technique is effective for improvement of the linearity and other performances.

In this paper, we define a discretized chaotic map as a digital realization of a one-dimensional chaos map. As a concrete example, we consider a family of pseudochaotic sequences with maximum length, referred to as maximum length pseudochaotic sequences, obtained from a class of discretized piecewise linear map. A theoretical framework for designing maximum length pseudochaotic sequences of the discretized chaotic maps is obtained. These discretized piecewise linear chaotic maps can be used in the design of binary sequences with constant autocorrelation values for several time delays.

It is well known that the problem to solve a set of randomly chosen multivariate quadratic equations over a finite field is NP-hard. However, when the number of variables is much larger than the number of equations, it is not necessarily difficult to solve equations. In fact, when n ≥ m(m+1) (n,m are the numbers of variables and equations respectively) and the field is of even characteristic, there is an algorithm to find one of solutions of equations in polynomial time (see [Kipnis et al., Eurocrypt '99] and also [Courtois et al., PKC '02]). In the present paper, we propose two new algorithms to find one of solutions of quadratic equations; one is for the case of n ≥ (about) m2-2m 3/2+2m and the other is for the case of n ≥ m(m+1)/2+1. The first one finds one of solutions of equations over any finite field in polynomial time, and the second does with O(2m) or O(3m) operations. As an application, we also propose an attack to UOV with the parameters given in 2003.

This paper presents a novel technique to realize Karnin et al.'s (k,n)-threshold schemes over binary field extensions as a software. Our realization uses the matrix representation of finite fields and matrix-vector multiplications, and enables rapid operations in software implementation. The theoretical evaluation and computer simulation reveal that our realization of Karnin et al.'s scheme achieves much faster processing time than the ordinary symbol oriented realization of the scheme. Further, we show that our realization has comparable performance to the existing exclusive-OR-based fast schemes of Fujii et al. and Kurihara et al.

Locator/ID Separation Protocol (LISP) is an efficient proposal for solving the severe routing scalability problems existing in the current IPv4-based Internet and the future IPv6-based Internet. However, the basic LISP architecture does not specify how to support mobility in detail. As mobility is a fundamental issue faced by the future Internet, LISP mobility architecture (LISP-MN) was proposed recently to extend LISP to support mobility. Nevertheless, LISP-MN is a host-based mobility approach which requires software changes in end systems. To some extent, such a design breaks the primary design principles of LISP, which is a network-based protocol and requires no modification to the hosts. In addition, LISP-MN faces the same inherent problems as other host-based approaches (e.g., MIPv4, MIPv6), such as handover latency, packet loss, and signalling overhead. To solve the above problems, this paper proposes MobileID, which is a network-based localized mobility approach for LISP. In our design, a mobile node is not aware of its mobility and does not participate in handover signalling. Instead, the network takes the responsibility for managing mobility on behalf of the mobile node. We present a general overview of MobileID architecture, and introduce the detailed protocol operations in terms of the basic MobileID handover process and the route optimization procedures. Furthermore, we describe a MobileID analytic model, and compare MobileID handover performance with three representative mobility solutions, i.e., LISP-MN, MIPv6 and PMIPv6. Numerical results show the superior performance of MobileID. The handover latency of MobileID is much lower than those of LISP-MN and MIPv6, and it becomes lower than that of PMIPv6 in case of a long wireless link delay.

Since video traffic has become a dominant flow component on the Internet, the Future Internet and New Generation Network must consider delay guarantees as a key feature in their designs. Using the stochastic network optimization, optimal control policies are designed for delay-constrained traffic in single-hop wireless networks. The resulting policy is a scheduling policy with delay guarantees. For a cross-layer design that involves both flow control and scheduling, the resulting policy is a flow control and scheduling policy that guarantees delay constraints and achieves utility performance within O(1/V) of the optimality.

This letter proposes a new scheduling method to improve scheduling efficiency of EPON. The proposed method uses a credit pool for each optical network unit (ONU) and for each service class. For high scheduling efficiency, the credit pool of an ONU can be negative amount to utilize the unused ONU credits. Also the proposed method dynamically excludes the lowest service class from scheduling to decrease a transmission cycle length. Using simulations, we show that the proposed method is better than the existing methods in mean delay.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

In this paper, we propose a new interference alignment (IA) scheme that jointly designs the linear transmitter and receiver for the 2-user MIMO X channel system, using minimum total mean square error criterion, subject to each transmitter power constraint. We show that transmitters and receivers under such criteria could be realized through a joint iterative algorithm. Considering the imperfection of channel state information (CSI), we also extend the minimum mean square error interference alignment schemes for the MIMO X channel with CSI estimation error. A robust iterative algorithm which is insensitve to CSI estimation error is proposed. Simulation results are also provided to demonstrate the proposed algorithm.

We propose a scheduling method called SCQ (Smoothly Changing Queue) which can control service rate by bulk size of video streaming services such as IPTV and VoD. Since SCQ allows queue length to change smoothly, video streaming services can be stably provided with low jitter. Queueing analysis results show that SCQ can more stably deliver video streaming with low jitter and loss than existing AQMs or queue length-based rate control methods.

Recently, the 3-dimensional (3-D) vertical Floating Gate (FG) type NAND flash memory cell arrays with the Extended Sidewall Control Gate (ESCG) was proposed [7]. Using this novel structure, we successfully implemented superior program speed, read current, and less interference characteristics, by the high Control Gate (CG) coupling ratio with less interference capacitance and highly electrical inverted S/D technique. However, the process stability of the ESCG structure has not been sufficiently confirmed such as the variations of the physical dimensions. In this paper, we intensively investigated the electrical dependency according to the physical dimensions of ESCG, such as the line and spacing of ESCG and the thickness of barrier oxide. Using the 2-dimentional (2-D) TCAD simulations, we compared the basic characteristics of the FG type flash cell operation, in the aspect of program speed, read current, and interference effect. Finally, we check the process window and suggest the optimum target of the ESCG structure for reliable flash cell operation. From above all, we confirmed that this 3-dimensional vertical FG NAND flash memory cell arrays using the ESCG structure is the most attractive candidate for terabit 3-D vertical NAND flash cell array.

We have studied the transport property of the Vertical MOSFET (V-MOSFET) with an impurity from the viewpoint of quantum electron dynamics. In order to obtain the position dependence of impurity for the electron transmission property through the channel of the V-MOSFET, we solve the time-dependent Shrodinger equation in real space mesh technique We reveal that the impurity in the source edge can assist the electron transmission from the source to drain working as a wave splitter. In addition, we also reveal the effect of an impurity in the surface of pillar is limited because of its dimensionality. Furthermore, we obtained that the electron injection from the source to the channel becomes difficult due to the energy difference between the subbands of the source and the channel. These results enable us to obtain the guiding principle to design the V-MOSFET in the 10 nm pillar. The results enable us to obtain the guiding principle to design the V-MOSFET beyond 20 nm design rule.

A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.

The fabricated 1.55 µm high power superluminescent light emitting diodes (SLEDs) with 115 mW maximum output power and 3 dB bandwidth of 50 nm, using active multi-mode interferometer (MMI), showed high coupling efficiency of 66% into single-mode fiber, which resulted in maximum fiber-coupled power of 77 mW.