High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

The effect of DC offset on multi-input multi-output (MIMO) direct transceivers with adaptive modulation (AM) is discussed in this paper. A variable-rate variable-power (VRVP) AM system with perfect channel state information (P-CSI) at both the transmitter and receiver in a MIMO scenario is considered. The DC offset is modeled as a zero mean complex Gaussian distributed random variable. By this modeling of the DC offset, the analytical expression for degraded bit error rate (BER) is derived. To derive this analytical expression, we establish a reasonable approximation. The good agreement between the analytical and simulation results shows that the approximation is valid and confirms the accuracy of the analytical expressions. Moreover, an approach to improve the degraded BER in these systems is introduced. For this purpose, we introduce a design for AM MIMO systems that takes account of DC offset and its effectiveness is confirmed. Throughput analysis for the AM MIMO system in the presence of DC offset is presented in this paper too. An analytical expression for throughput is derived and approximated to a simpler equation. At last, throughput results are compared to the simulation outcomes.

A novel random number generation method based on chaotic sampling of regular waveform is proposed. A high speed IC truly random number generator based on this method is also presented. Simulation and experimental results, verifying the feasibility of the circuit, are given. Numerical binary data obtained according to the proposed method pass the four basic tests of FIPS-140-2, while experimental data pass the full NIST-800-22 random number test suite without post-processing.

It is known that composable secure commitments, that is, concurrent non-malleable commitments exist in the plain model, based only on standard assumptions such as the existence of claw-free permutations or even one-way functions. Since being based on the plain model, the deniability of them is trivially satisfied, and especially the latter scheme satisfies also adaptivity, hence it is adaptive-deniable-concurrent non-malleable. However, those schemes cannot be said to be practically efficient. We show a practically efficient (string) adaptive-deniable-concurrent commitment scheme is possible under a global setup model, called the Global CRS-KR model.

A novel computational method is proposed to investigate electromagnetic scattering problems. It is error controllable and reliable simulation in time domain can be performed. We apply the proposed method to analysis of transient scattering from open-ended structures and discuss scattering mechanisms.

We present a new methodology for constructing an efficient identification scheme, and based on it, we propose a lightweight identification scheme whose computational and storage costs are sufficiently low even for cheap devices such as RFID tags. First, we point out that the efficiency of a scheme with statistical zero-knowledgeness can be significantly improved by enhancing its zero-knowledgeness to perfect zero-knowledge. Then, we apply this technique to the Girault-Poupard-Stern (GPS) scheme which has been standardized by ISO/IEC. The resulting scheme shows a perfect balance between communication cost, storage cost, and circuit size (computational cost), which are crucial factors for implementation on RFID tags. Compared to GPS, the communication and storage costs are reduced, while the computational cost is kept sufficiently low so that it is implementable on a circuit nearly as small as GPS. Under standard parameters, the prover's response is shortened 80 bits from 275 bits to 195 bits and in application using coupons, storage for one coupon is also reduced 80 bits, whereas the circuit size is estimated to be larger by only 335 gates. Hence, we believe that the new scheme is a perfect solution for fast authentication of RFID tags.

This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.

In this paper, a scheme for constructing the flat frequency spectrum of interleaved frequency division multiple access (IFDMA) is proposed. Since IFDMA is one of the single carrier modulation schemes, the frequency spectrum components are fluctuated and depend on the information data sequence. Even if IFDMA modulation scheme makes frequency spectrum dispersive for obtaining frequency diversity gain, frequency diversity gain is reduced by the fluctuation of frequency spectrum. In addition, in decision directed channel estimation (DDCE), which achieves good channel estimation accuracy in fast fading environment, the accuracy of channel transfer function estimated at the significant attenuated frequency component is much degraded. In the proposed technique, a random phase sequence is multiplied to the information data sequence for constructing the flat frequency spectrum. As a result, the frequency diversity gain is enlarged and the accuracy of channel estimation by DDCE is improved. Furthermore, we consider the blind estimation technique for the random phase sequence selected by transmitter. We show the effects of the proposed scheme by computer simulation.

The patching technique has been used for reducing initial waiting time in VOD services. Traditionally the technique has been applied to fixed segment NVOD scheduling. However, variable segment NVOD scheduling is known to have a better server bandwidth and less initial waiting time. In this paper, we propose a new scheduling algorithm for a true VOD service by incorporating the patching technique into variable segment NVOD scheduling. Our algorithm provides jitter-free playback while minimizing the use of the patching bandwidth. We present the proof of the correctness of our algorithm.

The safety applications for cooperative driving in VANETs, typically require the dissemination of safety-related information to all vehicles with high reliability and a strict timeline. However, due to the high vehicle mobility, dynamic traffic density, and a self-organized network, Safety message dissemination has a special challenge to efficiently use the limited network resources to satisfy its requirements. With this motivation, we propose a novel broadcasting protocol referred to as congestion awareness multi-hop broadcasting (CAMB) based loosely on a TDMA-like transmission scheduling scheme. The proposed protocol was evaluated using different traffic scenarios within both a realistic channel model and an 802.11p PHY/MAC model in our simulation. The simulation results showed that the performance of our CAMB protocol was better than those of the existing broadcasting protocols in terms of channel access delay, packet delivery ratio, end-to-end delay, and network overhead.

In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

Both multiplexing and multi-user diversity are exploited based on Round Robin (RR) scheduling to achieve tradeoffs between average throughput and fairness in distributed antenna systems (DAS). Firstly, a parallel Round Robin (PRR) scheduling scheme is presented based on the multi-user multiplexing in spatial domain to enhance the throughput, which inherits the excellent fairness performance of RR. Then a parallel grouping Round Robin (PGRR) is proposed to exploit multi-user diversity based on PRR. Due to the integration of multi-user diversity and multi-user multiplexing, a great improvement of throughput is achieved in PGRR. However, the expense of the improvement is at the degradation of fairness since the "best channel criteria" is used in PGRR. Simulations verify analysis conclusions and show that tradeoffs between throughput and fairness can be achieved in PGRR.

We edit in this paper several archives on the research and development in the field of microwave circuit technology in Japan, that originated with the invention of Yagi-Uda antenna in 1925, together with generally unknown historical topics in the period from the 1920s up until the end of World War II. As the main subject, we investigate the origin and evolution of the Multiply Split-Anode Magnetron, and clarify that the basic magnetron technology had been established until 1939 under the direction of Yoji Ito in cooperation of expert engineers between the Naval Technical Institute (NTI) and the Nihon Musen Co., while the Cavity Magnetron was invented by Shigeru Nakajima of the Nihon Musen Co. in May 1939, and further that physical theory of the Multiply Split-Anode Cavity Magnetron Oscillation and the design theory of the Cavity Magnetron were established in collaboration between the world-known physicists and the expert engineers at the NTI Shimada Laboratory in the wartime. In addition, we clarify that Sin-itiro Tomonaga presented the Scattering Matrix representation of Microwave Circuits, and others. The development mentioned above was carried out, in strict secrecy, in an unusual wartime situation up until 1945.

In distributed spectrum sensing, spatially distributed sensors perform radio frequency (RF) sensing and forward the result to a fusion center (FC). Cognitive radio (CR) obtains spectral information from the FC. Distributed spectrum sensing facilitates reliable discovery of spectrum opportunity while providing enhanced protection to legacy systems. The overall performance of distributed spectrum sensing depends both on the quality of sensing at the individual sensors and the forwarding scheme from the individual sensors. In this aspect the choice of media access control (MAC) plays a significant role. We can improve the system performance by optimizing the MAC and the spectrum sensing parameters jointly. In this paper we propose an enhanced MAC scheme based on existing scheduled MAC protocols to yield a high performance distributed spectrum sensing. To demonstrate our idea, we provide computer simulation by considering energy detection based distributed spectrum sensors and IEEE 802.15.4 PHY and MAC parameters.

Scattering characteristics of a domain wall displacement detection (DWDD) disk with a control layer were investigated by finite-difference time-domain (FDTD) analysis. DWDD is one of the high-density storage technologies of magneto-optical (MO) disks and the control layer is used to suppress ghost signals due to a rear process. The effects of the control layer on the scattering characteristics were studied.

This paper proposes two algorithms to balance energy consumption among sensor nodes by distributing the workload of image compression tasks within a cluster on wireless sensor networks. The main point of the proposed algorithms is to adopt the energy threshold, which is used when we implement the exchange and/or assignment of tasks among sensor nodes. The threshold is well adaptive to the residual energy of sensor nodes, input image, compressed output, and network parameters. We apply the lapped transform technique, an extended version of the discrete cosine transform, and run length encoding before Lempel-Ziv-Welch coding to the proposed algorithms to improve both quality and compression rate in image compression scheme. We extensively conduct computational experiments to verify the our methods and find that the proposed algorithms achieve not only balancing the total energy consumption among sensor nodes and, thus, increasing the overall network lifetime, but also reducing block noise in image compression.

Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.

This paper presents a systemic analysis for phase noise performances of differential cross-coupled LC oscillators by using Hajimiri and Lee's model. The effective impulse sensitivity functions (ISF) for each noise source in the oscillator is mathematically derived. According to these effective ISFs, the phase noise contribution from each device is figured out, and phase noise contributions from the device noise in the vicinity of the integer multiples of the resonant frequency, weighted by the Fourier coefficients of the effective ISF, are also calculated. The explicit closed-form expression for phase noise of the oscillator is definitely determined. The validity of the phase noise analysis is verified by good simulation agreement.

In this letter, a new feedback equalization scheme to suppress inter-carrier interference (ICI) in an OFDM system using scattered pilot is investigated. On a fast fading channel severe ICI occurs due to a Doppler shift and it deteriorates a bit error rate (BER) seriously because of small subcarrier spacing. In an ISDB-T receiver the equalization is mainly processed in a frequency domain because the scattered pilot is transmitted over the subcarriers. However, the frequency domain equalization may not suppress severe ICI in the case of the fast fading channel with a large Doppler shift. The proposed equalization scheme uses the scattered pilot symbols transformed in a time domain as the reference signal for feedback taps. Numerical results through computer simulation show that the proposed scheme improves the BER performance especially with low carrier-to-noise ratio (CNR) conditions.

Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to protect cryptography circuits from them. RSA is one of the most important cryptography algorithms because it effectively realizes a public-key cryptography system. RSA is extensively used but conventional scan-based side-channel attacks cannot be applied to it because it has a complicated algorithm. This paper proposes a scan-based side-channel attack which enables us to retrieve a secret key in an RSA circuit. The proposed method is based on detecting intermediate values calculated in an RSA circuit. We focus on a 1-bit time-sequence which is specific to some intermediate values. By monitoring the 1-bit time-sequence in the scan path, we can find out the register position specific to the intermediate value and we can know whether this intermediate value is calculated or not in the target RSA circuit. We can retrieve a secret key one-bit by one-bit from MSB to LSB. The experimental results demonstrate that a 1,024-bit secret key used in the target RSA circuit can be retrieved using 30.2 input messages within 98.3 seconds and its 2,048-bit secret key can be retrieved using 34.4 input within 634.0 seconds.