We introduce new computer algorithm of multiple alignment as an application of "Simulated Annealing" method. Simulated Annealing has been applied to some combinational optimization problems such as travelling salesman problem. After giving short mathematical explanation of this method, we construct genetic distance and matrix corresponding to the object function in the annealing theory for the multiple alignment. Our method is better than other alignment in the sense that we obtain a result having a smaller value for the genetic distance. We discuss further development along on new method.

An integrated CAD/CAM system for MMIC development has been firstly realized, which consists of electron beam direct drawing, microwave circuit simulator, pattern generator and RF &DC on-wafer automatic measurement subsystems, connected through an Ethernet LAN. The system can develop not only new MMICs and their element devices, but also their accurate simulation models quickly and efficiently. Preliminary successful applications of this system have been demonstrated by DC-HFET with a 0.25 µm T-shaped gate electrode and MMIC low-noise amplifiers operating at X- and L-bands.

Novel, very small-size multilayer MMIC's using miniature microstrip lines on a thin dielectric film, as well as the features of the multilayer structure, are presented. Very narrow-width thin-film transmission lines, meander-like configurations, line crossovers, and vertical connections, which are effective for significant chip-size reduction and flexible layout, are realized and utilized in a 2.5-3 µmN-layer dielectric film structure. 180-degree and 90-degree hybrids and umltiport Wilkinson dividers, which are implemented in small areas of 0.1 mm2 and 1.7 mm2, are presented. Furthermore, layout flexibility in the multilayer structure is demonstrated by implementing distributed amplifiers into the layers.

This paper describes the design of a 38-GHz high power MMIC amplifier using an improved load-pull technique. We improved the load-pull technique accuracy by using MMIC transtormers to match the input and output impedances of a GaAs MESFET to about 50 ohms. We used this technique to measure the large-signal load impedance of a FET with a 600-µm-wide gate. Using the data obtained, we developed an MMIC amplifier composed of two of these FET cells. At 38 GHz, the amplifier has an output power of 23.5 dBm for a 1 dB gain compression level.

Novel transmission line structures for multilayer MMICs, which are constructed with thin dielectric layers on a GaAs wafer surface, are theoretically and experimentally investigated. Five thin film transmission line structures are discussed in this paper: (1) Microstrip lines, (2) Inverted microstrip lines, (3) Triplate lines, (4) Trapezoidal microstrip lines and (5) Valley microstrip lines. These transmission line structures are fabricated using thin polyimide films and chemical etching.

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

An intermediate-frequency-combining (IF-combining) polarization diversity using frequency conversion is proposed. The proposed diversity requires no phase controller as opposed to the conventional IF-combining diversity. It has been theoretically clarified that this diversity has polarization insensitive bit-error-rate (BER) characteristics. The effectiveness has been confirmed by experiments in which the sensitivity dependence on the polarization is suppressed to within 0.8dB and a stable 101km fiber transmission at 600Mbit/s is achieved.

The optimal coding strategy for signal detection in the correlated gaussian noise is established for the distributed sensors system with essentially zero transmission rate constraint. Specifically, we are able to obtain the same performance as in the situation of no restriction on rate from each sensor terminal to the fusion center. This simple result contrasts with the previous ad hoc studies containing many unnatural assumptions such as the independence of noises contaminating received signal at each sensor. For the design of optimal coder, we can use the classical Levinson-Wiggins-Robinson fast algorithm for block Toeplitz matrix to evaluate the necessary weight vector for the maximum-likelihood detection.

This paper discusses and evaluates, from the viewpoints of definition, analysis, and performance, frequency assignment schemes that enable the efficient assignment of multiple-bandwidth carriers on the transponder in SCPC/FDMA systems with demand assignment operation. The system considered handles carriers of two different bandwidths, and assigns only consecutive slots on the transponder band to broadband carriers. Three types of frequency assignment schemes are proposed, each of which incorporates one or both of two assignment concepts: (1) pre-establishment of assignment priorities on the transponder band, and (2) establishment of broadband slots to guide broadband carrier assignment. Following a definition of the schemes, equations are derived to theoretically analyze performance factors such as call loss for the narrowband and broadband carriers, and system utilization efficiency. Finally, theoretical performance calculated for various traffic and system conditions are presented and evaluated, for the purpose of comparison between the three schemes. Computer simulation results are also presented, to demonstrate the accuracy of the derived equations and to supply data for models too large for theoretical computation. Main results obtained are as follows. (1) Regardless of traffic or system conditions, the assignment scheme incorporating both assignment priorities and broadband slots shows the best performance in terms of broadband call loss and system utilization efficiency. (2) The establishment of broadband slots improves performance when the ratio of broadband traffic to the total traffic volume is high, but worsens performance when the narrowband traffic ratio is higher. (3) All aspects of performance improve with the increase of the total number of assignable slots on the transponder band.

An extremely accurate and very wide-band quadrature modulator IC fabricated on a single chip using bipolar technology is presented. The characteristics of this quadrature modulator IC are much superior to conventional ones (modulation phase error and deviation from quadrature is about 1/10), and this IC is applicable to high modulation schemes such as 256 QAM. In this circuit, the phase difference between local signals input to each of two balanced modulators is detected by a phase detector, and a variable phase shifter in the local port is controlled automatically by the detected signals. This, along with the use of a wide-band variable phase shifter, enables the phase difference between the local signals input to the balanced modulators to be adaptively controlled to 90 degrees in wide frequency bands. In addition, a design method for the balanced modulators to obtain small modulation phase error is described. Based on this design method, a highly accurate quadrature modulator IC was fabricated, in which two balanced modulators, the phase detector, and the variable phase shifter were integrated on a single chip. Phase deviation from quadrature in the local signals was reduced to less than 0.3 degrees in the wide frequency bands of more tham 60 MHz. The modulation phase error of the balanced modulators wes less than 0.2 degrees at 140 MHz, and less than 2.5 degrees at up to 1.3 GHz.

A fast scan-line algorithm for a raster-scan graphics display is proposed based on an observation that a sequence of successive image frames in animation mostly consists of still objects with relatively few moving objects. In the proposed algorithm, successive images are generated using the background image composed of still objects only, and moving image composed only of moving objects. The color of each pixel in the successive images is then determined by one, which is nearer from eye, between the two candidate pixels, where one is from the background image and the other is from the moving image. The background image is generated once in the whole process, while the moving image is generated for each time frame using an interpolation of two images generated at the start and end time of the given time interval. For the purpose of fast shadow generation, we classify the shadows into three groups, i.e., still shadows generated by still objects on still objects, moving shadows generated by moving objects on still objects, and composite shadows generated by both still objects and moving objects on moving objects. These shadows can be generated very quickly by utilizing the frame coherence. According to the experimental results, a speed up factor of 3.2 to 12.8, depending on the percentage of the moving objects among all objects, was obtained using our algorithm, compared to the conventional scheme not utilizing the frame-to-frame image coherence.

The F-matrix expressions of inverted-L-type four-terminal networks, each involving an element with the power-law conductivity σ(ω)ωa (0a1) connected to a resistance R, an inductance L or a capacitance C, were derived using the standard procedures of Laplace transformation, indicating that the exponents of the complex angular frequency s, so far limited to the integers for the transmission circuits with finite elements, can be extended to the real numbers. The responses to a step voltage calculated show hysteretic behavior reflecting the resistance-capacitance ambivalent nature of the power-law conductivity.

General estimation technique using covariance information is proposed for white Gaussian and white Gaussian plus coloured observation noises in linear stationary stochastic systems. Namely, autocovariance data of signal and coloured noise appear in a semi-degenerate kernel, which represents functional expression of the autocovariance data, in the current technique. Then the signal is estimated by directly using autocovariance data of signal and coloured noise. On the other hand, in the previous technique, the covariance information is expressed in the form of a semi-degenerate kernel, but its elements do not include any autocovariance data.

This paper attempts to account for intelligibility of practices-based learning (so-called 'learning control') for skill refinement from the viewpoint of Newtonian mechanics. It is shown from an axiomatic approach that an extended notion of passivity for the residual error dynamics of robots plays a crucial role in their ability of learning. More precisely, it is shown that the exponentially weighted passivity with respect to residual velocity vector and torque vector leads the robot system to the convergence of trajectory tracking errors to zero with repeating practices. For a class of tasks when the endpoint is constrained geometrically on a surface, the problem of convergence of residual tracking errors and residual contact-force errors is also discussed on the basis of passivity analysis.

Threre are two types of nonlinear associative silicon retinas. One is a sparse Hopfield type neural network which is called a H-type retina and the other is its dual network which is called a DH-type retina. The input information sequences of H-type and HD-type retinas are given by nodes and links as voltages and currents respectively. The error correcting capacity (minimum basin of attraction) of H-type and DH-type retinas is decided by the minimum numbers of links of cutset and loop respectively. The operation principle of the regeneration is based on the voltage or current distribution of the neural field. The most important nonlinear operation in the retinas is a dynamic quantization to decide the binary value of each neuron output from the neighbor value. Also, the edge is emphasized by a line-process. The rates of compression of H-type and DH-type retinas used in the simulation are 1/8 and (2/3) (1/8) respectively, where 2/3 and 1/8 mean rates of the structural and binarizational compression respectively. We could have interesting and significant simulation results enough to make a chip.

The problems of cache coherency in multiprocessor systems are directly related to their architectural structures. Small scale multiprocessor systems have focused on the use of bus based memory interconnection networks using centrally shared memory and a sequential consistency model for coherency. This has limited scalability to but a few tens of processors due to the limited bus bandwidth used for both coherency updates and memory traffic. Recently, large scale multiprocessor systems have been proposed that use general interconnection networks and distributed shared memory. These architectures have been proposed using weak consistency models and various directory map schemes to hide the overhead for coherency maintenance within the memory hieratchy, interconnection network or process context switch latencies. The coherency and memory traffic are still maintained over the same interconnection network. In this paper, we present the architecture of a new general purpose medium scale multiprocessor system. This Cache Coherent Multiprocessor System (C2MP), supports distributed shared memory using a general memory interconnection network for memory traffic and a separate bus based coherency interconnection network for coherency maintenance. Through the use of a special directory based coherency protocol and cache oriented distributed coherency controllers, direct cache-to-cache coherency maintenance is performed over the dedicated coherency bus. This minimizes coherency updates to only those processor nodes needing coherency maintenance. An aggressive sequential coherncy model is used, which reduces the hardware penalty to support an ideal sequential consistency programmers model. The system can scale up to 256-512 processors depending on the degree of shared data and is expected to have higher per processor utilization in this range than currently proposed medium and large scale multiprocessor systems. The C2MP system is analyzed utilizing a Generalized Timed Petri-Net model of a processor node. A stochastic model for internode interactions over the general memory interconnection network and coherency bus are used . The model of the proposed architecture is analyzed under steady-state conditions for varying system work load parameters.

The purpose of the present paper is to review a state of the art of nonlinear analysis with the self-validating numerical method. The self-validating numerics based method provides a tool for performing computer assisted proofs of nonlinear problems by taking the effect of rounding errors in numerical computations rigorously into account. First, Kantorovich's approach of a posteriori error estimation method is surveyed, which is based on his convergence theorem of Newton's method. Then, Urabe's approach for computer assisted existence proofs is likewise discussed. Based on his convergence theorem of the simplified Newton method, he treated practical nonlinear differential equations such as the Van der Pol equation ahd the Duffing equation, and proved the existence of their periodic and quasi-periodic solutions by the self-validating numerics. An approach of the author for generalization and abstraction of Urabe's method are also discribed to more general funcional equations. Furthermore, methods for rigorous estimation of rounding errors are surveyed. Interval analytic methods are discussed. Then an approach of the author which uses rational arithmetic is reviewed. Finally, approaches for computer assisted proofs of nonlinear problems are surveyed, which are based on the self-validating numerics.

Artificial neurons and neural networks have been shown to perform Principal Component Analysis (PCA) when gradient ascent learning rules are used, which are related to the constrained maximization of statistical objective functions. Due to their parallelism and adaptivity to input data, such algorithms and their implementations in neural networks are potentially useful in feature extraction and data compression. In the companion paper(9), two such learning rules were derived from two criteria, the Subspace Criterion and the Weighted Subspace Criterion. It was shown that the only solutions to the latter problem are dominant eigenvectors of the data covariance matrix, which are the basis vectors of PCA. It was suggested by a simulation that the corresponding learning algorithm converges to these eigenvectors. A homogeneous neural network implementation was proposed for the algorithm. The learning algorithm is analyzed here in detail and it is shown that it can be approximated by a continuous-time differential equation that is obtained by averaging. It is shown that the asymptotically stable limits of this differntial equation are the eigenvectors. The neural network learning algorithm is further extended to a case in which each neuron has a sigmoidal nonlinear feedback activity function. Then no parameters specific to each neuron are needed, and the learning rule is fully homogeneous.

Principal Component Analysis (PCA) is a useful technique in feature extraction and data compression. It can be formulated as a statistical constrained maximization problem, whose solution is given by unit eigenvectors of the data covariance matrix. In a practical application like image compression, the problem can be solved numerically by a corresponding gradient ascent maximization algorithm. Such on-line algoritms can be good alternatives due to their parallelism and adaptivity to input data. The algorithms can be implemented in a local and homogeneous way in learning neural networks. One example is the Subspace Network. It is a regular layer of parallel artificial neurons with a learning rule that is completely homogeneous with respect to the neurons. However, due to the complete homogeneity, the learning rule does not converge to the unique basis given by the dominant eigenvectors, but any basis of this eigenvector subspace is possible. In many applications like data compression, the subspace is not sufficient but the actual eigenvectors or PCA coefficient vectors are needed. A new criterion, called the Weighted Subspace Criterion, is proposed, which makes a small symmetry-breaking change to the Subspace Criterion. Only the true eigenvectors are solutions. Making the corresponding change to the learning rule of the Subspace Network gives a modified learning rule, which can be still implemented on a homogeneous network architecture. In learning, the weight vectors will tend to the true eigenvectors.

This paper discusses the design, implementation, and performance of a bus-connected multiprocessor, called Presto, for a Rete-based production system. To perform a match, which is a major phase of a production system, a Presto match scheme exploits the subnetworks that are separated by the top two-input nodes and the token flow control at these nodes. Since parallelism of a production system can only increase speed 10-fold, the aim is to do so efficiently on a low-cost, compact bus-connected multi-processor system without shared memory or cache memory. The Presto hardware consists of up to 10 processisng elements (PEs), each comprising a commercial microprocessor, 4 Mbytes of local memory, and two kinds of newly developed ASIC chips for memory control and bus control. Hierarchical system software is provided for developing interpreter programs. Measurement with 10 PEs shows that sample programs run 5-7 times faster.