In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

In this letter, a simple and robust synchronization algorithm for second generation terrestrial digital video broadcasting (DVB-T2) receivers is proposed. In the proposed detection scheme, the coarse symbol timing is estimated by decimating a correlation output to give a sharper peak timing detection metric. Such a design can improve the timing synchronization accuracy as well as enhance its robustness to frequency selective channels.

The second generation digital terrestrial broadcasting system (DVB-T2) is the first broadcasting system employing MISO (Multiple-Input Single-Output) algorithms. The potential MISO gain of this system has been roughly predicted through simulations and field tests. Of course, the potential MISO SFN gain (MISO-SFNG) differs according to the simulation conditions, test methods, and measurement environments. In this paper, network gains of SISO-SFN and MISO-SFN are theoretically derived. Such network gains are also analyzed with respect to the receive power imbalance and coverage distances of SISO and MISO SFN. From the analysis, it is proven that MISO-SFNG is always larger than SISO SFN gain (SISO-SFNG) in terms of the achievable SNR. Further, both MISO-SFNG and SISO-SFNG depend on the power imbalance, but the network gains are constant regardless of the modulation order. Once the field strength of the complete SFN is obtained by coverage planning tools or field measurements, the SFN service coverage can be precisely calibrated by applying the closed-form SFNG formula.

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3 dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.

A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 1012 fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.

The purpose of our study is to develop an algorithm that would enable the automated detection of lacunar infarct on T1- and T2-weighted magnetic resonance (MR) images. Automated identification of the lacunar infarct regions is not only useful in assisting radiologists to detect lacunar infarcts as a computer-aided detection (CAD) system but is also beneficial in preventing the occurrence of cerebral apoplexy in high-risk patients. The lacunar infarct regions are classified into the following two types for detection: "isolated lacunar infarct regions" and "lacunar infarct regions adjacent to hyperintensive structures." The detection of isolated lacunar infarct regions was based on the multiple-phase binarization (MPB) method. Moreover, to detect lacunar infarct regions adjacent to hyperintensive structures, we used a morphological opening processing and a subtraction technique between images produced using two types of circular structuring elements. Thereafter, candidate regions were selected based on three features -- area, circularity, and gravity center. Two methods were applied to the detected candidates for eliminating false positives (FPs). The first method involved eliminating FPs that occurred along the periphery of the brain using the region-growing technique. The second method, the multi-circular regions difference method (MCRDM), was based on the comparison between the mean pixel values in a series of double circles on a T1-weighted image. A training dataset comprising 20 lacunar infarct cases was used to adjust the parameters. In addition, 673 MR images from 80 cases were used for testing the performance of our method; the sensitivity and specificity were 90.1% and 30.0% with 1.7 FPs per image, respectively. The results indicated that our CAD system for the automatic detection of lacunar infarct on MR images was effective.

A novel ratio-oriented definition based on 2T2R (Two transistors & two phase change resistors) phase change memory (PCM) cell structure is proposed to gain a high density by multilevel storage. In this novel solution, no reference is needed and good robustness remains still as conventional 2T2R, which is crucial when feature size scales to nanometer technology node. A behavioral SPICE model together with a preliminary simulation proves the idea to be feasible, and further optimization has been carried out. In addition, based on the ratio-oriented definition, a simpler and faster Error Control Coding (ECC) can be realized with n-Error-detection feasible.

We investigate the enhancement of the optical nonlinearity and the limit of the improvement of the response speed in CdSxSe1-x microcrystallites by measuring the effective optical nonlinear cross section (σeff), the energy decay time (T1) and the dephasing time in two kinds of semiconductor microcrystallites of CdS0.12Se0.8 microcrystallites embedded in alkaline multi-component glasses (CdSSeMs) and CdSe microcrystallites embedded in SiO2 thin film (CdSeMs). As the average radius of CdSSeMs decreases from 10 to 1 nm, the values of σeff and T1 gradually change from 2.610-16 to 1.110-16 cm2 and from dozens picoseconds to 4 psec, respectively. The size dependence of CdSSEMs shows that the energy level structure in the microcrystallite with a radius of less than a few nanometers is a two-level system, in which σeff is proportional to T2. The carrier recombination time (τ) of CdSSeMs with the average radius of 1 nm is estimated to 2 psec. As the average radius of a CdS0.12Se0.8 microcrystallite decreases from 9 to 3 nm, the values of T2 gradually change from 640 to 230 fsec at 18 K, respectively. The size and temperature dependences of T2 for the CdSSeMs show that there is the discrepancy between the theory and the measured T2. The discrepancy showes the presence of the acoustic-phonon-assisted relaxation processes other than the pure-dephasing processes. It is indicated that T2 becomes long by reducing the excessive acoustic-phonon-assisted relaxation processes, and that the longer T2 might enhance σeff. We investigate the enhancement of σeff in CdSeMs by making T2 longer. The τ, σeff, and T2 of CdSeM an average radius of 3 nm are 40 psec, 4.510-15 cm2, and 150 fsec at room temperature. The σeff is ten times as large as that of CdSSeM sample at the same average radius and the enhancement of σeff can be considered to be caused by the longer T2.

This paper addresses the variation of the attenuation characteristics of the Specific Absorption Rate (SAR) in a lossy medium as a function of the distance between an antenna and the medium with different EM-source sizes. Analysis and measurements were performed using a dipole antenna at 900 MHz and a COST244 cubic phantom. From this, an empirical equation has been derived, representing the attenuation characteristics of the SAR. The equation takes into consideration an energy loss due to the spatial spread of electromagnetic waves. In the case where an antenna is placed more than λ/2π away from the medium, the attenuation characteristics of the SAR are those obtained from plane waves in the lossy medium. In the case where a half-wavelength dipole antenna is located close to the medium, at a distance of less than λ/2π, the attenuation characteristics of the SAR are calculated from an equation that includes a loss caused by the spread of energy as a cylindrical wave. Moreover, when the length of antenna is short, it is found that a spatial attenuation factor appropriate to a spherical wave should be taken into account.

This paper proposes an enhanced RBF network that enhances learning algorithms between input layer and middle layer and between middle layer and output layer individually for improving the efficiency of learning. The proposed network applies ART2 network as the learning structure between input layer and middle layer. And the auto-tuning method of learning rate and momentum is proposed and applied to learning between middle layer and output layer, which arbitrates learning rate and momentum dynamically by using the fuzzy control system for the arbitration of the connected weight between middle layer and output layer. The experiment for the classification of number patterns extracted from the citizen registration card shows that compared with conventional networks such as delta-bar-delta algorithm and the ART2-based RBF network, the proposed method achieves the improvement of performance in terms of learning speed and convergence.

In this paper, an effective index structure for dynamic main memory database systems, which we call the T2-tree, is presented. A notion of a thread pointer is introduced to overcome some of the limitations of the T-tree and the T*-tree. There are several advantages to this structure. First, the T2-tree reduces the number of rotate operations and the overhead required for balancing the tree by restraining new node creation and deletion. Second, the T2-tree shows good performance for sequential search of range queries as these requests can be effectively handled using the successor pointer. Finally, the T2-tree allows for higher space utilization amplicating the aforementioned benefits. These advantages are obtained with minimal changes to the existing T-tree structure. Experimental studies showing evidence of the benefits of the T2-tree are also presented.

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6 104 seconds. It was also predicted that low voltage operation was possible if the device parameters were optimized.