The input impedance of an antenna fluctuates because of various usage conditions, which causes a mismatch between an internal circuit and an antenna. An automatic matching system solves this problem, then this paper presents a reconfigurable impedance tuner that has a set of fixed capacitors controlled by switching p-i-n diodes. A fast control algorithm for selecting the appropriate conditions of an impedance tuner is proposed and mounted on FPGA to demonstrate the performance.

Recently, for more efficient filtering of XML data, YFilter system has been suggested to exploit the prefix commonalities that exist among path expressions. Sharing the prefix commonality gives the benefit of improving filtering performance through the tremendous reduction in filtering machine size. However, exploiting the postfix commonality can also be useful for an XML filtering situation. For example, when a stream of XML messages does not have any defined schema, or users cannot remember the defined schema exactly, users often use the partial matching path queries which begins with the descendant axis ("//"), e.g., '//science/article/title', '//entertainment/article/title', and '//title'. If so, the registered XPath queries are most likely to have the postfix commonality, e.g., the sample queries share the partial path expressions 'article/title' and 'title'. Therefore, in this paper, we introduce a bottom-up filtering approach exploiting the postfix commonality against the top-down approach of YFilter exploiting the prefix commonality. Some experimental results show that our method has better filtering performance when registered XPath queries mainly consist of the partial matching path queries with the postfix commonality.

This paper presents design and analysis of an Automatic Repeat reQuest (ARQ) scheme for enhancing the throughput and reliability of broadband wireless access systems. The impact of ARQ is emphasized in terms of early error recovery, when Internet data applications and the TCP protocol are considered over a point-to-multipoint fixed wireless system. A selective repeat type ARQ scheme is designed and analyzed through extensive, realistic modeling and simulation of the entire network protocol stack and the wireless channel. The system-wide impact of ARQ design is quantified in terms of end-to-end delay, throughput and SNR gain and in all these metrics, significant performance improvement is observed. Enhanced features, namely, Segmentation and Reassembly (SAR) and Bitmap Compression, are proposed and shown to reduce the overhead costs.

A deterministic pushdown automaton (dpda) having just one stack symbol is called a deterministic restricted one-counter automaton (droca). When it accepts an input by empty stack, it is called strict. This paper is concerned with a subclass of real-time strict droca's, called Szilard strict droca's, and studies the problem of identifying the subclass in the limit from positive data. The class of languages accepted by Szilard strict droca's coincides with the class of Szilard languages (or, associated languages) of strict droca's and is incomparable to each of the class of regular languages and that of simple languages. After providing some properties of languages accepted by Szilard strict droca's, we show that the class of Szilard strict droca's is polynomial time identifiable in the limit from positive data in the sense of Yokomori. This identifiability is proved by giving an exact characteristic sample of polynomial size for a language accepted by a Szilard strict droca. The class of very simple languages, which is a proper subclass of simple languages, is also proved to be polynomial time identifiable in the limit from positive data by Yokomori, but it is yet unknown whether there exists a characteristic sample of polynomial size for any very simple language.

To improve the computation efficiency of the application specific instruction-set processor (ASIP), a strategy of hardware/software collaborative design is usually utilized. In this process, the auto-customization of specific instruction set has always been a key part to support the automated design of ASIP. The key issue of this problem is how to effectively reduce the huge exponential exploration space in the instruction identification process. To address this issue, we first formulate it as a feasible sub-graph enumeration problem under multiple constraints, and then propose a fast instruction identification algorithm based on a new model called basic convex pattern (BCP). The kernel technique in this algorithm is the transformation from the graph exploration to the formula-based computations. The experimental results have indicated that the proposed algorithm has a distinct reduction in the execution time.

In this paper, we propose a new model of automatically constructing an acronym dictionary. The proposed model generates possible acronym candidates from a definition, and then verifies each acronym-definition pair with a Naive Bayes classifier based on web documents. In order to achieve high dictionary quality, the proposed model utilizes the characteristics of acronym generation types: a syllable-based generation type, a word-based generation type, and a mixed generation type. Compared with a previous model recognizing an acronym-definition pair in a document, the proposed model verifying a pair in web documents improves approximately 50% recall on obtaining acronym-definition pairs from 314 Korean definitions. Also, the proposed model improves 7.25% F-measure on verifying acronym-definition candidate pairs by utilizing specialized classifiers with the characteristics of acronym generation types.

Two variable gain amplifiers (VGAs) that adopt new approximated exponential equations are proposed in this paper. The dB-linear range of the proposed VGAs is extended more than what the approximated exponential equations predict by a bias circuit technique that adopts negative feedback. The proposed VGAs feature wide gain variation, low-power, high linearity, wide control signal range, and small chip size. One of the proposed VGAs is fabricated in 0.18 µm CMOS technology and measurements show a gain variation of 83 dB (-3647 dB) with a gain error of less than 2 dB, and P1 dB/IIP3 from -55/8 to -20/20.5 dBm, while consuming an average current of 3.4 mA from a 1.8 V supply; the chip occupies 0.4 mm2. The other VGA is simulated in 0.18 µm CMOS technology and simulations show a gain variation of 91 dB (-4150 dB), and P1 dB/IIP3 from -50/-25 to -33/0 dBm, while consuming an average current of 1.5 mA from a 1.8 V supply.

An all CMOS variable gain amplifier (VGA) which features wide dB-linear gain range per stage (45 dB), low power consumption (1.32 mW), small chip size (0.13 mm2), and low supply voltage (1.2 V) is described. The dB-linear range is extended by reducing the supply voltage of the conventional V-to-I converter. The two-stage VGA implemented in 0.18 µm CMOS offers 90 dB of gain variation, 3 dB bandwidth of greater than 21 MHz, and max/min input IP3 and P1 dB, respectively, of -5/-42 and -12/-50 dBm.

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

Encapsulating critical computation subgraphs as application-specific instruction set extensions is an effective technique to enhance the performance of embedded processors. However, the addition of custom functional units to the base processor is required to support the execution of these custom instructions. Although automated tools have been developed to reduce the long design time needed to produce a new extensible processor for each application, short time-to-market, significant non-recurring engineering and design costs are issues. To address these concerns, we introduce an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. To support this feature, custom functional units (CFUs) are replaced by a reconfigurable functional unit (RFU). The proposed RFU is based on a matrix of functional units which is multi-cycle with the capability of conditional execution. A quantitative approach is utilized to propose an efficient architecture for the RFU and fix its constraints. To generate more effective custom instructions, they are extended over basic blocks and hence, multiple exits custom instructions are proposed. Conditional execution has been added to the RFU to support the multi-exit feature of custom instructions. Experimental results show that multi-exit custom instructions enhance the performance by an average of 67% compared to custom instructions limited to one basic block. A maximum speedup of 4.7, compared to a general embedded processor, and an average speedup of 1.85 was achieved on MiBench benchmark suite.

We have developed a visual entertainment system called "Future Cast" which enables anyone to easily participate in a pre-recorded or pre-created film as an instant CG movie star. This system provides audiences with the amazing opportunity to join the cast of a movie in real-time. The Future Cast System can automatically perform all the processes required to make this possible, from capturing participants' facial characteristics to rendering them into the movie. Our system can also be applied to any movie created using the same production process. We conducted our first experimental trial demonstration of the Future Cast System at the Mitsui-Toshiba pavilion at the 2005 World Exposition in Aichi Japan.

In this paper, we propose a PLSA-based language model for sports-related live speech. This model is implemented using a unigram rescaling technique that combines a topic model and an n-gram. In the conventional method, unigram rescaling is performed with a topic distribution estimated from a recognized transcription history. This method can improve the performance, but it cannot express topic transition. By incorporating the concept of topic transition, it is expected that the recognition performance will be improved. Thus, the proposed method employs a "Topic HMM" instead of a history to estimate the topic distribution. The Topic HMM is an Ergodic HMM that expresses typical topic distributions as well as topic transition probabilities. Word accuracy results from our experiments confirmed the superiority of the proposed method over a trigram and a PLSA-based conventional method that uses a recognized history.

In this paper, signal processing techniques which can be applied to automatic speech recognition to improve its robustness are reviewed. The choice of signal processing techniques is strongly dependent on the scenario of the applications. The analysis of scenario and the choice of suitable signal processing techniques are shown through two examples.

This paper describes a robust automatic speech recognition (ASR) system with less computation. Acoustic models of a hidden Markov model (HMM)-based classifier include various types of hidden factors such as speaker-specific characteristics, coarticulation, and an acoustic environment, etc. If there exists a canonicalization process that can recover the degraded margin of acoustic likelihoods between correct phonemes and other ones caused by hidden factors, the robustness of ASR systems can be improved. In this paper, we introduce a canonicalization method that is composed of multiple distinctive phonetic feature (DPF) extractors corresponding to each hidden factor canonicalization, and a DPF selector which selects an optimum DPF vector as an input of the HMM-based classifier. The proposed method resolves gender factors and speaker variability, and eliminates noise factors by applying the canonicalzation based on the DPF extractors and two-stage Wiener filtering. In the experiment on AURORA-2J, the proposed method provides higher word accuracy under clean training and significant improvement of word accuracy in low signal-to-noise ratio (SNR) under multi-condition training compared to a standard ASR system with mel frequency ceptral coeffient (MFCC) parameters. Moreover, the proposed method requires a reduced, two-fifth, Gaussian mixture components and less memory to achieve accurate ASR.

This paper presents an automatic adjustment of the transfer function of phase locked loop (PLL). The time constants and the gain factor of the transfer function are adjusted without opening the loop of PLL. The time constant adjustment is performed using a replica of the 1st order RC low pass filter and the gain factor is adjusted by detecting the open loop gain at the unity gain frequency. These adjustments are automatically carried out using a digitally controlled capacitance array and a digitally controlled charge pump. The proposed calibration can reduce the bandwidth error of 30% to 5% and the gain error of 7 dB to 1 dB.

In this letter, a Tomlinson-Harashima precoding (THP) scheme is proposed for the downlink of multiuser MIMO systems with multiple antennas at each receiver. Assuming single data stream communication for each user, joint transmitter and receiver design is done to maximize the signal to noise ratio (SNR) for each user. Furthermore, a heuristic user ordering algorithm is proposed to optimize the encoding order and improve the bit error rate (BER) performance. Simulation results have shown that the proposed approach is superior to some existing precoding schemes.

Human's ability to perceive elevation of a sound and distinguish whether a sound is coming from the front or rear strongly depends on the monaural spectral features of the pinnae. In order to realize an effective virtual auditory display by HRTF (head-related transfer function) customization, the pinna responses were isolated from the median HRIRs (head-related impulse responses) of 45 individual HRIRs in the CIPIC HRTF database and modeled as linear combinations of 4 or 5 basic temporal shapes (basis functions) per each elevation on the median plane by PCA (principal components analysis) in the time domain. By tuning the weight of each basis function computed for a specific height to replace the pinna response in the KEMAR HRIR at the same height with the resulting customized pinna response and listening to the filtered stimuli over headphones, 4 individuals with normal hearing sensitivity were able to create a set of HRIRs that outperformed the KEMAR HRIRs in producing vertical effects with reduced front/back ambiguity in the median plane. Since the monaural spectral features of the pinnae are almost independent of azimuthal variation of the source direction, similar vertical effects could also be generated at different azimuthal directions simply by varying the ITD (interaural time difference) according to the direction as well as the size of each individual's own head.

The performance of single-carrier (SC) transmission in a frequency-selective fading channel degrades due to a severe inter-symbol interference (ISI). Using frequency-domain equalization (FDE) based on the minimum mean square error (MMSE) criterion can improve the bit error rate (BER) performance of SC transmission. However, the residual ISI after FDE limits the performance improvement. In this paper, we propose a joint use of Tomlinson-Harashima precoding (THP) and FDE to remove the residual ISI. An approximate conditional BER analysis is presented for the given channel condition. The achievable average BER performance is evaluated by Monte-Carlo numerical computation method using the derived conditional BER. The BER analysis is confirmed by computer simulation of the signal transmission.

For a coarse grain dynamic reconfigurable processing unit cooperating with a general purpose processor, a context selection method, which can reduce total execution cycles of a given program, is proposed. The method evaluates context candidates from a given program, in terms of reduction in cycles by exploiting parallel and pipeline execution of the reconfigurable processor. According to this evaluation measure, the method selects appropriate contexts for the dynamic reconfigurable processing unit. The proposed method is implemented on the framework of COINS project. For several example programs, the generated codes are evaluated by a software simulator in terms of execution cycles, and these results prove the effectiveness of the proposed method.

This letter proposes a novel method of large-scale IP traffic matrix estimation which is based on Partial Flow Measurement and Fratar Model (PFMFM). Firstly, we model OD flows as Fratar model and introduce the constrained relations between traffic matrix and link loads. By combining partial flow measurement, we can get a good prior value of network tomography. Then a good estimation of traffic matrix is attained with the modified network tomography method. Finally, we use the real data [8] from network Abilene to validate our method. In contrast to TomoGravity [1], the results show that our method improves remarkably and the estimation of traffic matrix is closer to real data, and especially when the flow is small and changes dramatically, the estimation is better.