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3361-3380hit(5900hit)

  • TSK-Based Linguistic Fuzzy Model with Uncertain Model Output

    Keun-Chang KWAK  Dong-Hwa KIM  

     
    PAPER-Computation and Computational Models

      Vol:
    E89-D No:12
      Page(s):
    2919-2923

    We present a TSK (Takagi-Sugeno-Kang)-based Linguistic Fuzzy Model (TSK-LFM) with uncertain model output. Based on the Linguistic Model (LM) proposed by Pedrycz, we develop a comprehensive design framework. The main design process is composed of the automatic generation of the contexts, fuzzy rule extraction by Context-based Fuzzy C-Means (CFCM) clustering, connection of bias term, and combination of TSK and linguistic context. Finally, we contrast the performance of the presented models with other models for coagulant dosing process in a water purification plant.

  • Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique

    Nobuhiro DOI  Takashi HORIYAMA  Masaki NAKANISHI  Shinji KIMURA  

     
    PAPER-System Level Design

      Vol:
    E89-A No:12
      Page(s):
    3427-3434

    High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.

  • Influence of ADC Nonlinearity on the Performance of an OFDM Receiver

    Manabu SAWADA  Hiraku OKADA  Takaya YAMAZATO  Masaaki KATAYAMA  

     
    PAPER

      Vol:
    E89-B No:12
      Page(s):
    3250-3256

    This paper discusses the influence of the nonlinearity of analog-to-digital converters (ADCs) on the performance of orthogonal frequency division multiplexing (OFDM) receivers. We evaluate signal constellations and bit error rate performances while considering quantization errors and clippings. The optimum range for an ADC input amplitude is found as a result of the trade-off between quantization error and the effects of clipping. In addition, it is shown that the peak-to-average power ratio (PAPR) of the signal is not a good measure of the bit error rate (BER) performance, since the largest peaks occur only with very low probabilities. The relationship between the location of a subcarrier and its performance is studied. As a result, it is shown that the influence of the quantization error is identical for all subcarriers, while the effects of clipping depend on the subcarrier frequency. When clipping occurs, the BER performance of a subcarrier near the center frequency is worse than that near the edges.

  • Novel Compact Microstrip Dual-Mode Ring Resonator Wideband Bandpass Filter with Significantly Improved Stopband Property

    Peng CAI  Zhewang MA  Xuehui GUAN  Yoshio KOBAYASHI  Tetsuo ANADA  

     
    PAPER-Passive Circuits/Components

      Vol:
    E89-C No:12
      Page(s):
    1858-1864

    A novel wideband bandpass filter with improved stopband characteristics is presented in this paper. Dual-mode square ring resonator is used in the proposed filter. New formulas based on the even- and odd-mode analysis are derived to facilitate the design of transmission zeros of the square ring resonator. A short-circuited stub and a piece of aperture-enhanced parallel-coupled lines are introduced to the input and output of the resonator to lower the passband return loss and widen the stopband of the filter significantly. The filter has a 50% fractional bandwidth, is compact in configuration, and shows remarkably improved performance compared with previously reported filters of the same kind. The measured filtering response shows a good agreement with the simulated result.

  • Design and Verification of On-Chip Impedance-Matching Circuit Using Transmission-Line Theory for 2.4 GHz-Band Wireless Receiver Front-End

    Haruichi KANAYA  Ramesh K. POKHAREL  Fuminori KOGA  Keiji YOSHIDA  

     
    PAPER-Passive Circuits/Components

      Vol:
    E89-C No:12
      Page(s):
    1888-1895

    Recently, spiral inductors have widely been used instead of resistors in the design of matching circuits to enhance the thermal noise performance of a wireless transceiver. However, such elements usually have low quality factor (Q) and may encounter the self-resonance in microwave-frequency band which permits its use in higher frequencies, and on the other hand, they occupy the large on-chip space. This paper presents a new design theory for the impedance-matching circuits for a single-chip SiGe BiCMOS receiver front-end for 2.4 GHz-band wireless LAN (IEEE 802.11b). The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverter. The prototype front-end receiver is designed, fabricated and tested. A few of the measured results to verify the design theory are presented.

  • A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC

    Zhenyu LIU  Yang SONG  Takeshi IKENAGA  Satoshi GOTO  

     
    PAPER-Integrated Electronics

      Vol:
    E89-C No:12
      Page(s):
    1928-1936

    One full search variable block size motion estimation (VBSME) architecture with integer pixel accuracy is proposed in this paper. This proposed architecture has following features: (1) Through widening data path from the search area memories, m processing element groups (PEG) could be scheduled to work in parallel and fully utilized, where m is a factor of sixteen. Each PEG has sixteen processing elements (PE) and just costs 8.5K gates. This feature provides users more flexibility to make tradeoff between the hardware cost and the performance. (2) Based on pipelining and multi-cycle data path techniques, this architecture can work at high clock frequency. (3) The memory partition number is greatly reduced. When sixteen PEGs are adopted, only two memory partitions are required for the search area data storage. Therefore, both the system hardware cost and power consumption can be saved. A 16-PEG design with 4832 search range has been implemented with TSMC 0.18 µm CMOS technology. In typical work conditions, its maximum clock frequency is 261 MHz. Compared with the previous 2-D architecture [9], about 13.4% hardware cost and 5.7% power consumption can be saved.

  • Rate-Distortion Optimized Selection of Motion Vectors for Video Transmission over Packet-Loss Channels

    Jing YANG  Xiangzhong FANG  

     
    LETTER-Multimedia Systems for Communications

      Vol:
    E89-B No:12
      Page(s):
    3494-3496

    The selection of motion vectors plays an important role in the error propagation process between inter-frames. In this letter, an end-to-end prediction error calculation method is proposed and is used for the rate-distortion optimized selection of motion vectors. Simulation results show that the robustness of encoded video streams under error-prone environment is improved.

  • Sequence Set with Three Low Correlation Zones

    Xiaoming TAO  Chao ZHANG  Jianhua LU  

     
    LETTER-Fundamental Theories for Communications

      Vol:
    E89-B No:12
      Page(s):
    3421-3424

    Sequence set with Three Zero Correlation Zones (T-ZCZ) is applied in Quasi-Synchronized CDMA communication system to reduce the Multiple Access Interference (MAI) and Inter Symbol Interference (ISI). In this letter, we present a class of sequence set with Three Low Correlation Zones (T-LCZ), which has more sequences and flexibility than T-ZCZ sequence set. Moreover, the theoretical bound on T-LCZ sequences is derived for estimating the performance of such sequence set.

  • Electron Transfer Mediated Biosensor with Plasma-Polymerized Film Containing Redox Site

    Hitoshi MUGURUMA  Hideyuki UEHARA  

     
    PAPER-Bioelectronics and Sensors

      Vol:
    E89-C No:12
      Page(s):
    1781-1785

    An electron transfer mediated amperometric enzyme biosensor based on a plasma-polymerized thin film of dimethylaminomethylferrocene (DMAMFc) is reported. A nanoscale thin polymer film containing a redox mediator was plasma-deposited directly onto an electrode with physisorbed glucose oxidase (GOD). Since the redox sites were introduced in the vicinity of the reaction centers of GOD, a highly efficient electron transfer system was formed in which almost all the reaction centers of GOD were connected to redox sites of the polymer matrix. The advantages of this strategy were: no need for prior or further chemical modification of the enzyme molecules, and simplicity of design compared with the use of a conventional polymer matrix. Moreover, the fact that the film deposition was performed using a microfabrication-compatible organic plasma promised great potential for high-throughput production of bioelectronic devices.

  • Novel Blind Adaptive Equalization over Doubly-Selective Fading Channels

    Mi-Kyung OH  Yeong-Hyeon KWON  Dong-Jo PARK  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E89-B No:12
      Page(s):
    3463-3466

    A new receiver structure that combines the constant modulus algorithm (CMA) and the Kalman filter (KF) is investigated to exploit the advantages of both algorithms; simple implementation of blind algorithms, and excellent tracking ability, respectively. The proposed scheme achieves faster convergence and adaptability to the channel variation, which is verified through comparative simulations in doubly-selective (time- and frequency-selective) fading channels.

  • A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

    Yang SONG  Zhenyu LIU  Takeshi IKENAGA  Satoshi GOTO  

     
    PAPER-VLSI Architecture

      Vol:
    E89-A No:12
      Page(s):
    3594-3601

    A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25), a clock frequency of 266 MHz can be achieved.

  • A Parallel Network Emulation Method for Evaluating the Correctness and Performance of Applications

    Yue LI  Chunxiao XING  Ying HE  

     
    PAPER

      Vol:
    E89-D No:12
      Page(s):
    2897-2906

    Network emulation system constructs a virtual network environment which has the characteristics of controllable and repeatable network conditions. This makes it possible to predict the correctness and performance of proposed new technology before deploying to Internet. In this paper we present a methodology for evaluating the correctness and performance of applications based on the PARNEM, a parallel discrete event network emulator. PARNEM employs a BSP based real-time event scheduling engine, provides flexible interactive mechanism and facilitates legacy network models reuse. PARNEM allows detailed and accurate study of application behavior. Comprehensive case studies covering bottleneck bandwidth measurement and distributed cooperative web caching system demonstrate that network emulation technology opens a wide range of new opportunities for examining the behavior of applications.

  • Iterative Frequency-Domain Soft Interference Cancellation for Multicode DS- and MC-CDMA Transmissions and Performance Comparison

    Koichi ISHIHARA  Kazuaki TAKEDA  Fumiyuki ADACHI  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E89-B No:12
      Page(s):
    3344-3355

    Frequency-domain equalization (FDE) based on the minimum mean square error (MMSE) criterion can significantly improve the BER performance of DS- and MC-CDMA systems in a severe frequency-selective fading channel. However, since the frequency-distorted signal cannot be completely equalized, the residual inter-code interference (ICI) limits the BER performance improvement. 4G systems must support much higher variable rate data services. Orthogonal multicode transmission technique has flexibility in offering variable rate services. However, the BER performance degrades as the number of parallel codes increases. In this paper, we propose an iterative frequency-domain soft interference cancellation (IFDSIC) scheme for multicode DS- and MC-CDMA systems and their achievable BER performances are evaluated by computer simulation.

  • Finish Time Predictability of Earliest Deadline Zero Laxity Algorithm for Multiprocessor Real-Time Systems

    Sangchul HAN  Heeheon KIM  Xuefeng PIAO  Minkyu PARK  Seongje CHO  Yookun CHO  

     
    LETTER-System Programs

      Vol:
    E89-D No:12
      Page(s):
    2981-2984

    This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

  • A Radio Synchronization Technique for Asynchronous Broadband Networks

    Sungho JEON  Sanghoon LEE  

     
    LETTER-Transmission Systems and Transmission Equipment for Communications

      Vol:
    E89-B No:12
      Page(s):
    3433-3437

    A radio synchronization technique that dispenses with GPS (Global Positioning System) for OFDM (Orthogonal Frequency Division Multiplexing)-based broadband networks is described. UMTS (Universal Mobile Telecommunications System) employs three main mechanisms, a node, transport channel and radio interface synchronization. The RNC (Radio Network Controller) is used as a key network component for the centralized synchronization mechanism. Here, we explore a more accurate and simpler asynchronous technique for broadband networks from the perspective of a distributed manner, where MSs (Mobile Stations) play an important role in timing adjustment. Propagation delay and the hierarchical synchronization mechanism are taken into account in the mathematical analysis.

  • Novel Phase-Continuous Frequency Hopping Control for a Direct Frequency Synthesizer Using a Quadrature Mixer Driven by Two DDSs

    Kenichi TAJIMA  Ryoji HAYASHI  Kenji ITOH  Yoji ISOTA  

     
    PAPER-Active Circuits/Devices/Monolithic Microwave Integrated Circuits

      Vol:
    E89-C No:12
      Page(s):
    1829-1835

    This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.

  • Automated Design of Analog Circuits Starting with Idealized Elements

    Naoyuki UNNO  Nobuo FUJII  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E89-A No:11
      Page(s):
    3313-3319

    This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

  • Design and Optimization of Microstrip Parallel-Coupled-Line Bandpass Filters Incorporating Impedance Matching

    Homayoon ORAIZI  Mahdi MORADIAN  Kazuhiro HIRASAWA  

     
    PAPER-Devices/Circuits for Communications

      Vol:
    E89-B No:11
      Page(s):
    2982-2989

    In this paper a new method for the design and optimization of microstrip parallel coupled-line bandpass filters is presented which allows for the specification of frequency bandwidths and arbitrary source and load impedance transformation. The even- and odd-mode theory and the relationships between impedance, transmission and scattering matrices and their properties are used to construct a positive definite error function using the insertion losses at discrete frequencies in the pass, transition and stop bands. The dispersion relations for the coupled line are also taken into account. The minimization of the error function determines the widths, gap spacings and lengths of the coupled-line filter, for the optimum design and realization of filter specifications. The proposed filter design and optimization method is coded by computer programs and the results of simulation, fabrication and testing of sample filters together with comparisons with available full-wave analysis softwares, indicate the efficacy of the proposed method. Filter design with up to 50% bandwidth and the design of shorter lengths of coupled line sections are achievable by the proposed method in part due to the incorporation of impedance matching.

  • Kalman Carrier Recovery Algorithm for High-Order QAM

    Dah-Chung CHANG  Wei-Tsen LIN  Yung-Fang CHEN  

     
    LETTER-Transmission Systems and Transmission Equipment for Communications

      Vol:
    E89-B No:11
      Page(s):
    3117-3119

    A new Kalman carrier synchronization algorithm is developed for high-order QAM transmission to reduce complexity compared to the conventional Kalman approach. The state model in the proposed algorithm employs only phase, instead of both phase and frequency, as in the conventional method. A reduced-observation model is also introduced to eliminate matrix operations in the Kalman recursions. Simulations results show that the one-state Kalman algorithm has better performance and lower complexity than the two-state Kalman algorithm. The cable modem downstream system is applied to demonstrate the effectiveness of the proposed algorithm.

  • Linear Precoding Based on Sub-Channel Permutation in Post-Combining MIMO-HARQ Systems

    Jinxia CHENG  Chi LIU  Shidong ZHOU  Ming ZHAO  Yan YAO  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E89-B No:11
      Page(s):
    3139-3142

    A powerful HARQ-based linear precoding scheme is proposed to utilize the flexibility of post-combining HARQ strategy in MIMO communications systems. The scheme selects the appropriate symbols and transmit powers for each eigen-mode to acquire more performance gains. Simulation results show that the proposed scheme achieves about 5.5 dB signal-to-noise ratio gains over original spatial multiplexing scheme at an average bit error rate of 10-4. Furthermore, the gap between the two schemes increases with the number of transmissions.

3361-3380hit(5900hit)