This paper deals with the scattering of transverse magnetic (TM) plane wave by a perfectly conductive surface made up of a periodic array of finite number of rectangular grooves. By the modal expansion method, the total scattering cross section pc is numerically calculated for several different numbers of grooves. It is then found that, when the groove depth is less than wavelenght, the total scattering cross section pc increases linearly proportional to the corrugation width W. But an exception takes place at a low grazing angle of incidence, where pc is proportional to Wα and the exponent α is less than 1. From these facts, it is concluded that the total scattering cross section pc must diverge but pc/W the total scattering cross section per unit surface must vanish at a low grazing limit when the number of grooves goes to infinity.

In order to introduce the burst firing, a nerve-cell dynamic feature, we extend the Inverse function Delayed model (ID model), which is the neuron model with ability to oscillate and has powerful ability on the information processing. This dynamics is discussed for the relation with the functional role of the brain and is characterized by repeated patterns of closely spaced action potentials. It is expected that the additional new characteristics add extra functions to neural networks. Using the relation between the ID model and reduced Hodgkin-Huxley model, we propose the neuron model with ability of burst. The proposed model excelled the ID model in solving the N-Queen problem. Additionally, the prototype chip for the burst ID model is implemented and measured.

For more efficient data transmissions, a new MLP/BP-based channel equalizer is proposed to compensate for multi-path fading in wireless applications. In this work, for better system performance, we apply the soft output and the soft feedback structure as well as the soft decision channel decoding. Moreover, to improve packet error rate (PER) and bit error rate (BER), we search for the optimal scaling factor of the transfer function in the output layer of the MLP/BP neural networks and add small random disturbances to the training data. As compared with the conventional MLP/BP-based DFEs and the soft output MLP/BP-based DFEs, the proposed MLP/BP-based soft DFEs under multi-path fading channels can improve over 3-0.6 dB at PER=10-1 and over 3.3-0.8 dB at BER=10-3.

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced by register relocation maintaining the circuit behavior and topology. In this paper, we propose a gate-level register relocation method to reduce the minimum feasible clock period. The proposed method is a greedy local circuit modification method. We prove that the proposed method achieves the clock period achieved by retiming with delay decomposition, if the delay of each element in the circuit is unique. Experiments show that the computation time of the proposed method and the number of registers of a circuit obtained by the proposed method are smaller than those obtained by the retiming method in the conventional synchronous framework.

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

The Self-Organizing Map (SOM) is an unsupervised neural network introduced in the 80's by Teuvo Kohonen. In this paper, we propose a method of simultaneously using two kinds of SOM whose features are different (the nSOM method). Namely, one is distributed in the area at which input data are concentrated, and the other self-organizes the whole of the input space. The competing behavior of the two kinds of SOM for nonuniform input data is investigated. Furthermore, we show its application to clustering and confirm its efficiency by comparing with the k-means method.

All optical analog-to-digital converter consisting of an optical polarization modulator using nonlinear phase shift and switches based on polarization is proposed. The principle of operation is discussed using Jones matrix. Optical polarization states through the system and limit of resolution are evaluated. The resolution is optimized by maintaining the polarization state in the converter and refining the polarization of incident sampling signal. Parallel usage of converter modules is proposed to increase the dynamic range, where cyclic nature of optical phase plays an important roll. Application to photonic routing of our converter is also proposed.

This paper proposes a new efficient method of characterizing a memory compiler in order to reduce the computation time and remove human error. The new features that make our method greatly efficient are the following three points: (1) high-speed circuit simulation of the whole memory module using a hierarchical LPE (Layout Parasitic Extractor) and a hierarchical circuit simulator, (2) automatic generation of circuit simulation input data from corresponding parameterized description termed the template file, and (3) carefully selected environmental conditions of circuit level simulator and minimizing the number of runs of it. We demonstrate the effectiveness of the proposed method by application to the single-port SRAM generators using 90 nm CMOS technology.

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.

3-D sound using head-related transfer functions (HRTFs) is applicable to embedded systems such as portable devices, since it can create spatial sound effect without multichannel transducers. Low-order modeling of HRTF with an IIR filter is effective for the reduction of the computational load required in embedded applications. Although modeling of HRTFs with IIR filters has been studied earnestly, little attention has been paid to sound movement with IIR filters, which is important for practical applications of 3-D sound. In this paper, a practical method for sound movement is proposed, which utilizes time-varying IIR filters and variable delay filters. The computational cost for sound movement is reduced by about 50% with the proposed method, compared to conventional low-order FIR implementation. In order to facilitate efficient implementation of 3-D sound movement, tradeoffs between the subjective quality of the output sound and implementation parameters such as the size of filter coefficient database and the update period of filter coefficients are also discussed.

Recently, we proposed space-time block coded-joint transmit/receive antenna diversity (STBC-JTRD) for narrow band transmission in a frequency-nonselective fading channel; it allows an arbitrary number of transmit antennas while limiting the number of receive antennas to 4. In this paper, we extend STBC-JTRD to the case of frequency-selective fading channels and propose frequency-domain STBC-JTRD for broadband direct sequence-spread spectrum (DSSS) signal transmission. A conditional bit error rate (BER) analysis is presented. The average BER performance in a frequency-selective Rayleigh fading is evaluated by Monte-Carlo numerical computation method using the derived conditional BER and is confirmed by computer simulation of the signal transmission. Performance comparison between frequency-domain STBC-JTRD transmission and joint space-time transmit diversity (STTD) and frequency-domain equalization (FDE) reception is also presented.

Adsorption of antibody protein (anti-human IgG) onto plasma-polymerized thin films (PPF) with nanoscale thickness was characterized by atomic force microscopy (AFM) and quartz crystal microbalance (QCM). The PPF surface is very flat (less than 1 nm roughness) and its properties (charge and wettability) can be easily changed while retaining the backbone structure. We focus on two types of surfaces: one is the pristine surface of hexamethyldisiloxane (HMDS) PPF (hydrophobic) and the other is an HMDS PPF surface with nitrogen-plasma treatment (hydrophilic and positive-charged surface). The AFM image showed that the antibody molecules were densely adsorbed onto both surfaces and individual antibody molecules could be observed. The QCM profiles show a corresponding tendency with the AFM images. These results indicate that the plasma polymerized film can be the suitable biointerface for the application of biosensor and bioassay.

Frequency-domain equalization (FDE) can take advantage of the frequency-selectivity of the channel to improve the transmission performance in a frequency selective fading channel. To further improve the transmission performance, the transmit diversity technique can be used. Cyclic delay transmit diversity (CDTD) can strengthen the frequency-selectivity while space-time transmit diversity (STTD) can achieve the antenna diversity gain. In this paper, we propose a 4-antenna space-time cyclic delay transmit diversity (STCDTD), which is a combination of 2-antenna STTD and 2-antenna CDTD schemes, for orthogonal multi-code direct sequence code division multiple access (DS-CDMA) using FDE. We evaluate the BER performance and the throughput performance by computer simulation and compare them with the original CDTD and STTD schemes.

This paper investigates a design and performance of 4-parallel MB-OFDM UWB receiver. The performance of the proposed MB-OFDM UWB receiver using a 4-parallel synchronization structure is degraded by 0.25 dB compared with that of a receiver using a 1-parallel synchronization structure in the maximum frequency/sampling clock offset tolerance in an AWGN channel. Considering other impairments, including imperfect synchronization algorithms, the effect of quantization error by the 4-parallel synchronization structure is negligible in a multi-path channel environment as well as in an AWGN channel, as identified in simulation results.

We propose a new cyclic postfix based orthogonal frequency division multiplexing (OFDM) system. The proposed system shows superior performance in symbol time synchronization while achieving channel estimation performance comparable to that of conventional cyclic prefix based OFDM system. In the proposed system, an identical postfix is generated at the end of each OFDM symbol by inserting pilot values amongst the data symbols in a frequency domain and performing Inverse Fast Fourier Transform (IFFT) operation on it. Robust time synchronization is achieved by auto- and cross-correlating the postfix. Also, time or frequency domain channel estimation can be realized by using properly designed postfix according to channel estimation method.

In nature an unbalanced clock tree exists in a SoC because the clock sinks of IPs have distinct input capacitive loads and internal delays. The construction of a bottom-up RLC clock tree with minimal clock delay and zero skew is crucial to ensure good SoC performance. This study proves that an RLC clock tree construction always has no zero skew owing to skew upward propagation. Specifically, this study proposes the insertion of two unit-size buffers associated with the binary search for a tapping point into each pair of subtrees to interrupt the non-zero skew upward propagation. This technique enables reliable construction of a buffered RLC clock tree with zero skew. The effectiveness of the proposed approach is demonstrated by assessing benchmarks.

This paper addresses the problem of inter-domain QoS routing with Service Level Agreements (SLA) for data transport between peering domains, using virtual-trunk type aggregates. The problem is formally stated and formulated in Integer Linear Programming. As a practical solution, we define the QoS_INFO extension to the BGP routing protocol, conveying three different QoS metrics (light load delay, assigned bandwidth and a congestion alarm), and a path selection algorithm using a combination of these metrics. We present simulation results of QoS_INFO, standard BGP, and BGP with the QoS_NLRI extension, and compare them with the optimal route set provided by the ILP formulation. The results show that our proposal yields better QoS than standard BGP or BGP with the QoS_NLRI extension, since it is able to efficiently avoid congested paths, and that the impact of QoS_INFO in route stability is relatively low.

Cache performance optimization is an important design consideration in building high-performance embedded processors. Unlike general-purpose microprocessors, embedded processors can take advantages of application-specific information in optimizing the cache performance. One of such examples is to use modified cache index bits (over conventional index bits) based on memory access traces from key target embedded applications so that the number of conflict misses can be reduced. In this paper, we present a novel fine-grained cache reconfiguration technique which allows an intra-program reconfiguration of cache index bits, thus better reflecting the changing characteristics of a program execution. The proposed technique, called dynamic reconfiguration of index bits (DRIB), dynamically changes cache index bits in the function level. This compiler-directed and fine-grained approach allows each function to be executed using its own optimal index bits with no additional hardware support. In order to avoid potential performance degradation by frequent cache invalidations from reconfiguring cache index bits, we describe an efficient algorithm for selecting target functions whose cache index bits are reconfigured. Our algorithm ensures that the number of cache misses reduced by DRIB outnumbers the number of cache misses increased from cache invalidations. We also propose a new cache architecture, Two-Level Indexing (TLI) cache, which further reduces the number of conflict misses by intelligently dividing indexing steps into two stages. Our experimental results show that the DRIP approach combined with the TLI cache reduces the number of cache misses by 35% over the conventional cache indexing technique.

This paper proposes a new blind adaptive MLSE equalizer for frequency selective mobile radio channels. The proposed equalizer performs channel estimation for each survivor path of the Viterbi algorithm (VA), and restricts the number of symbol candidates for the channel estimation in order to reduce prohibitive complexity. In such channel estimation, autocorrelation matrices of the symbol candidates are likely to become singular, which increases the estimation error. To cope with the singularity, the proposed equalizer employs a recursive channel estimation algorithm using the Moore-Penrose generalized inverse of the autocorrelation matrix. As another problem, the blind channel estimation can yield plural optimal estimates of a channel impulse response, and the ambiguity of the estimates degrades the BER performance. To avoid this ambiguity, the proposed equalizer is enhanced so that it can take advantage of the fractional sampling. The enhanced equalizer performs symbol-spaced channel estimation for each fractional sampling phase. This equalizer combines separate channel estimation errors, and provides the sum to the VA processor as the branch metric, which tremendously reduces the probability that a correct estimate turns into a false one. Computer simulation demonstrates the effectiveness of the proposed equalizers in the frequency selective fading channels.

In this paper, the authors propose a circularly polarized printed antenna combining a slot array antenna and a patch antenna, with dual-band operation. The proposed antenna has good isolation performance, is compact, and has simple configuration. This antenna is composed of two parts, a patch antenna (for Rx) on the top, and a slot array antenna (for Tx) on the bottom, respectively. The element layout is such that the lower radiation element is not hidden by the upper one for wide observation angle. Hence, both radiation elements can naturally radiate the targeted polarization. Both slot array and patch antenna are fed by electromagnetically coupled microstrip line feed. With such a configuration, it is possible to efficiently obtain good isolation characteristics for both frequency bands. Furthermore, this antenna can be easily composed and it is not necessary to use any feeding pin or via hole. The target of this antenna is mobile communications applications such as mobile satellite communications, base-station of wireless LAN, etc. Here, the design techniques are discussed and the numerical and experimental analyses are presented.