In this paper, we propose an automatic parameter adjustment method for audio equalizers using an interactive genetic algorithm (IGA). It is very difficult for ordinary users who are not familiar with audio devices to appropriately adjust the parameters of audio equalizers. We therefore propose a system that can automatically adjust the parameters of audio equalizers on the basis of user's evaluation of the reproduced sound. The proposed system utilizes an IGA to adjust the gains and Q values of the peaking filters included in audio equalizers. Listening test results demonstrate that the proposed system can appropriately adjust the parameters on the basis of the user's evaluation.

For an adaptive system identification filter with a stochastic input signal, a coefficient vector updated with an NLMS algorithm converges in the sense of ensemble average and the expected convergence vector has been revealed. When the input signal is periodic, the convergence of the adaptive filter coefficients has also been proved. However, its convergence vector has not been revealed. In this paper, we derive the convergence vector of adaptive filter coefficients updated with the NLMS algorithm in system identification for deterministic sinusoidal inputs. Firstly, we derive the convergence vector when a disturbance does not exist. We show that the derived convergence vector depends only on the initial vector and the sinusoidal frequencies, and it is independent of the step-size for adaptation, sinusoidal amplitudes, and phases. Next, we derive the expected convergence vector when the disturbance exists. Simulation results support the validity of the derived convergence vectors.

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18 µm technology, the core area of the processor is 3.47 mm2 and the maximum operating frequency can be up to 500 MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

Compressing a JPEG image twice will greatly decrease the values of some of its DCT coefficients. This effect can be easily detected by statistics methods. To defend this forensic method, we establish a model to evaluate the security and image quality influenced by the re-compression. Base on the model, an optimized adjustment of the DCT coefficients is achieved by Genetic Algorithm. Results show that the traces of double compression are removed while preserving image quality.

A novel method for automatically creating an optimum direction-of-arrival (DOA) estimation algorithm for a given radio environment using a genetic algorithm (GA) is proposed. DOA estimation algorithms are generally described by parameters and operators. The performance of a DOA estimation algorithm is evaluated using root mean square error (RMSE) through computer simulations. A GA searches for the combination of parameters and operators that gives the lowest RMSE. Because a GA can treat only bit strings, Polish notation is used to convert bit strings into a DOA estimation algorithm. A computer simulation showed that the proposed method can create a new angle spectrum function. The created angle spectrum function has higher resolution than the Capon method.

This paper presents two halftoning methods to improve efficiency in generating structurally similar halftone images using Structure Similarity Index Measurement (SSIM). Proposed Method I reduces the pixel evaluation area by applying pixel-swapping algorithm within inter-correlated blocks followed by phase block-shifting. The effect of various initial pixel arrangements is also investigated. Proposed Method II further improves efficiency by applying bit-climbing algorithm within inter-correlated blocks of the image. Simulation results show that proposed Method I improves efficiency as well as image quality by using an appropriate initial pixel arrangement. Proposed Method II reaches a better image quality with fewer evaluations than pixel-swapping algorithm used in Method I and the conventional structure aware halftone methods.

This study proposes an improved per-survivor-processing (PSP) scheme to tackle the phase error issue in the convolutionally coded OFDM systems. The proposed approach takes advantage of the trellis structure of the convolutional codes to compensate the symbol-time-offset (STO) caused phase error in frequency domain. Unlike the traditional PSP scheme which simply estimates the phase error by using a state-based horizontal process, the proposed approach develops an extra state-wise vertical process which selects the most likely phase estimate as the survival phase in each trellis stage and then accordingly align the phase of all states to this survival phase before moving to next trellis stage of the PSP scheme. With the vertical process, the resultant phase estimate is more reliable than that of the conventional PSP scheme and hence improve the accuracy in data decoding. Computer simulations confirm the validity of the proposed approach.

This paper develops a methodology of crosstalk analysis/measurement techniques for the design and fabrication of the MEMs (Micro-ElectroMichanical system) probe card. By introducing more ground pins into the connector pins, the crosstalk characteristics can be enhanced and a design guide for the parameters, such as pin's size and pitch is proposed to satisfy the given crosstalk limitation of -30 dB for reliable high speed signal transfer. The paper also presents a novel method to characterize scattering parameters of multiport interconnect circuits with a 4-port VNA (Vector Network Analyzer). By employing the re-normalization of scattering matrices with different reference impedances at other ports, data obtained from 4-port configuration measurements can be synthesized to build a full scattering matrix of the DUT (Device-Under-Test, MEMs probe connector pins). In comparison to the conventional 2-port VNA re-normalization method, proposed technique has two advantages: saving of measuring time, and enhanced accuracy even with open-ended unmeasured ports. A good agreement of the estimated and correct S parameters verifies the validness of the proposed algorithm.

Network-on-chip (NoC) architectures have emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). With the explosive growth in the usage of multimedia applications, it is expected that NoC serves as a multimedia server supporting multi-class services. In this paper, we propose a configuration algorithm for a hybrid bus-NoC architecture together with simulation results. Our target architecture is a hybrid bus-NoC architecture, called busmesh NoC, which is a generalized version of a hybrid NoC with local buses. In our BMNoC configuration algorithm, cores which have a heavy communication volume between them are mapped in a cluster node (CN) and connected by a local bus. CNs can have communication with each other via edge switches (ESes) and mesh routers (MRs). With this hierarchical communication network, our proposed algorithm can improve the latency as compared with conventional methods. Several realistic applications applied to our algorithm illustrate the better performance than earlier studies and feasibility of our proposed algorithm.

The minimized assumption generation has been recognized as an important improvement of the assume-guarantee verification method in order to generate minimal assumptions. The generated minimal assumptions can be used to recheck the whole component-based software at a lower computational cost. The method is not only fitted to component-based software but also has a potential to solve the state space explosion problem in model checking. However, the computational cost for generating the minimal assumption is very high so the method is difficult to be applied in practice. This paper presents an optimization as a continuous work of the minimized assumption generation method in order to reduce the complexity of the method. The key idea of this method is to find a smaller assumption in a sub-tree of the search tree containing the candidate assumptions using the depth-limited search strategy. With this approach, the improved method can generate assumptions with a lower computational cost and consumption memory than the minimized method. The generated assumptions are also effective for rechecking the systems at much lower computational cost in the context of software evolution. An implemented tool supporting the improved method and experimental results are also presented and discussed.

The linear complexity and its stability of periodic sequences are of fundamental importance as measure indexes on the security of stream ciphers and the k-error linear complexity reveals the stability of the linear complexity properly. Recently, Zhou designed an algorithm for computing the k-error linear complexity of 2pn periodic sequences over GF(q). In this paper, we develop a genetic algorithm to confirm that one can't get the real k-error linear complexity for some sequenes by the Zhou's algorithm. Analysis indicates that the Zhou's algorithm is unreasonable in some steps. The corrected algorithm is presented. Such algorithm will increase the amount of computation, but is necessary to get the real k-error linear complexity. Here p and q are odd prime, and q is a primitive root (mod p2).

It is shown that simple preprocessing on the reference signals in multichannel feedforward ANC system can improve the convergence performance of the adaptive ANC algorithm. A fast and efficient blind preprocessing algorithm in frequency domain is proposed to reduce the computational complexity even that the reference sensors are located far from the noise sources. The permutation problem at different frequency bin is also addressed and solved by an independent vector analysis algorithm. The basic principle and performance comparison are given to verify our conclusion.

Template matching for image sequences captured with a moving camera is very important for several applications such as Robot Vision, SLAM, ITS, and video surveillance systems. However, it is difficult to realize accurate template matching using only visual feature information such as HSV histograms, edge histograms, HOG histograms, and SIFT features, because it is affected by several phenomena such as illumination change, viewpoint change, size change, and noise. In order to realize robust tracking, structure information such as the relative position of each part of the object should be considered. In this paper, we propose a method that considers both visual feature information and structure information. Experiments show that the proposed method realizes robust tracking and determine the relationships between object parts in the scenes and those in the template.

A conical area evolutionary algorithm (CAEA) is presented to further improve computational efficiencies of evolutionary algorithms for bi-objective optimization. CAEA partitions the objective space into a number of conical subregions and then solves a scalar subproblem in each subregion that uses a conical area indicator as its scalar objective. The local Pareto optimality of the solution with the minimal conical area in each subregion is proved. Experimental results on bi-objective problems have shown that CAEA offers a significantly higher computational efficiency than the multi-objective evolutionary algorithm based on decomposition (MOEA/D) while CAEA competes well with MOEA/D in terms of solution quality.

This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

This paper proposes a new first-scan method for two-scan labeling algorithms. In the first scan, our proposed method first scans every fourth image line, and processes the scan line and its two neighbor lines. Then, it processes the remaining lines from top to bottom one by one. Our method decreases the average number of times that must be checked to process a foreground pixel will; thus, the efficiency of labeling can be improved.

One of the most important constraints in wireless sensor networks (WSN) is that their nodes, in most of the cases, are powered by batteries, which cannot be replaced or recharged easily. In these types of networks, data transmission is one of the processes that consume a lot of energy, and therefore the embedded routing algorithm should consider this issue by establishing optimal routes in order to avoid premature death and eventually having partitioned nodes network. This paper proposes a new routing algorithm for WSN called Micro-Economic Routing Algorithm (MERA), which is based on the microeconomic model of supply-demand. In such algorithm each node comprising the network fixes a cost for relay messages according to their residual battery energy; and before sending information to the base station, the node searches for the most economical route. In order to test the performance of MERA, we varied the initial conditions of the system such as the network size and the number of defined thresholds. This was done in order to measure the time span for which the first node dies and the number of information messages received by the base station. Using the NS-2 simulator, we compared the performance of MERA against the Conditional Minimum Drain Rate (CMDR) algorithm reported in the literature. An optimal threshold value for the residual battery is estimated to be close to 20%.

This letter investigates an iterative learning control with advanced output data (ADILC) scheme for non-minimum phase (NMP) systems when the number of NMP zeros is unknown. ADILC has a simple learning structure that can be applied to both minimum phase and NMP systems. However, in the latter case, it is assumed that the number of NMP zeros is already known. In this paper, we propose an ADILC scheme in which the number of NMP zeros is unknown. Based on input-to-output mapping, the learning starts from the relative degree. When the input becomes larger than a certain upper bound, we redesign the input update law which consists of the relative degree and the estimated value for the number of NMP zeros.

In this paper, we propose a novel architecture for large-scale regular expression matching, called dynamically reconfigurable bit-parallel NFA architecture (Dynamic BP-NFA), which allows dynamic loading of regular expressions on-the-fly as well as efficient pattern matching for fast data streams. This is the first dynamically reconfigurable hardware with guaranteed performance for the class of extended patterns, which is a subclass of regular expressions consisting of union of characters and its repeat. This class allows operators such as character classes, gaps, optional characters, and bounded and unbounded repeats of character classes. The key to our architecture is the use of bit-parallel pattern matching approach, in which the information of an input non-deterministic finite automaton (NFA) is first compactly encoded in bit-masks stored in a collection of registers and block RAMs. Then, the NFA is efficiently simulated by a fixed circuitry using bitwise Boolean and arithmetic operations consuming one input character per clock regardless of the actual contents of an input text. Experimental results showed that our hardwares for both string and extended patterns were comparable to previous dynamically reconfigurable hardwares in their performances.

In this paper, we propose an effective mutation operators for Cooperative Genetic Algorithm (CGA) to be applied to a practical Nurse Scheduling Problem (NSP). The nurse scheduling is a very difficult task, because NSP is a complex combinatorial optimizing problem for which many requirements must be considered. In real hospitals, the schedule changes frequently. The changes of the shift schedule yields various problems, for example, a fall in the nursing level. We describe a technique of the reoptimization of the nurse schedule in response to a change. The conventional CGA is superior in ability for local search by means of its crossover operator, but often stagnates at the unfavorable situation because it is inferior to ability for global search. When the optimization stagnates for long generation cycle, a searching point, population in this case, would be caught in a wide local minimum area. To escape such local minimum area, small change in a population should be required. Based on such consideration, we propose a mutation operator activated depending on the optimization speed. When the optimization stagnates, in other words, when the optimization speed decreases, the mutation yields small changes in the population. Then the population is able to escape from a local minimum area by means of the mutation. However, this mutation operator requires two well-defined parameters. This means that user have to consider the value of these parameters carefully. To solve this problem, we propose a periodic mutation operator which has only one parameter to define itself. This simplified mutation operator is effective over a wide range of the parameter value.