This paper presents a pivot-set generation algorithm for accelerating exact similarity search in a large-scale data set. To deal with the large-scale data set, it is important to efficiently construct a search index offline as well as to perform fast exact similarity search online. Our proposed algorithm efficiently generates competent pivots with two novel techniques: hierarchical data partitioning and fast pivot optimization techniques. To make effective use of a small number of pivots, the former recursively partitions a data set into two subsets with the same size depending on the rank order from each of two assigned pivots, resulting in a complete binary tree. The latter calculates a defined objective function for pivot optimization with a low computational cost by skillfully operating data objects mapped into a pivot space. Since the generated pivots provide the tight lower bounds on distances between a query object and the data objects, an exact similarity search algorithm effectively avoids unnecessary distance calculations. We demonstrate that the search algorithm using the pivots generated by the proposed algorithm reduces distance calculations with an extremely high rate regarding a range query problem for real large-scale image data sets.

To aim to achieve a high-performance computation for microwave simulations with low cost, small size machine and low energy consumption, a method of the FDTD dedicated computer has been investigated. It was shown by VHDL logical circuit simulations that the FDTD dedicated computer with a dataflow architecture has much higher performance than that of high-end PC and GPU. Then the remaining task of this work is large scale computations by the dedicated computer, since microwave simulations for only 18×18×Z grid space (Z is the number of girds for z direction) can be executed in a single FPGA at most. To treat much larger numerical model size for practical applications, this paper considers an implementation of a domain decomposition method operation of the FDTD dedicated computer in a single FPGA.

With an annual growth of billions of sensor-based devices, it is an urgent need to do stream mining for the massive data streams produced by these devices. Cloud computing is a competitive choice for this, with powerful computational capabilities. However, it sacrifices real-time feature and energy efficiency. Application-specific integrated circuit (ASIC) is with high performance and efficiency, which is not cost-effective for diverse applications. The general-purpose microcontroller is of low performance. Therefore, it is a challenge to do stream mining on these low-cost devices with scalability and efficiency. In this paper, we introduce an FPGA-based scalable and parameterized architecture for stream mining.Particularly, Dynamic Time Warping (DTW) based k-Nearest Neighbor (kNN) is adopted in the architecture. Two processing element (PE) rings for DTW and kNN are designed to achieve parameterization and scalability with high performance. We implement the proposed architecture on an FPGA and perform a comprehensive performance evaluation. The experimental results indicate thatcompared to the multi-core CPU-based implementation, our approach demonstrates over one order of magnitude on speedup and three orders of magnitude on energy-efficiency.

The song-level feature summarization is an essential building block for browsing, retrieval, and indexing of digital music. This paper proposes a local pooling method to aggregate the feature vectors of a song over the universal background model. Two types of local activation patterns of feature vectors are derived; one representation is derived in the form of histogram, and the other is given by a binary vector. Experiments over three publicly-available music datasets show that the proposed local aggregation of the auditory features is promising for music-similarity computation.

This paper deals with the constrained DAG shortest path problem (CDSP), which finds the shortest path on a given directed acyclic graph (DAG) under any logical constraints posed on taken edges. There exists a previous work that uses binary decision diagrams (BDDs) to represent the logical constraints, and traverses the input DAG and the BDD simultaneously. The time and space complexity of this BDD-based method is derived from BDD size, and tends to be fast only when BDDs are small. However, since it does not prioritize the search order, there is considerable room for improvement, particularly for large BDDs. We combine the well-known A* search with the BDD-based method synergistically, and implement several novel heuristic functions. The key insight here is that the ‘shortest path’ in the BDD is a solution of a relaxed problem, just as the shortest path in the DAG is. Experiments, particularly practical machine learning applications, show that the proposed method decreases search time by up to 2 orders of magnitude, with the specific result that it is 2,000 times faster than a commercial solver. Moreover, the proposed method can reduce the peak memory usage up to 40 times less than the conventional method.

Many real world optimization problems involving sets of agents can be modeled as Distributed Constraint Optimization Problems (DCOPs). A DCOP is defined as a set of variables taking values from finite domains, and a set of constraints that yield costs based on the variables' values. Agents are in charge of the variables and must communicate to find a solution minimizing the sum of costs over all constraints. Many applications of DCOPs include multiple criteria. For example, mobile sensor networks must optimize the quality of the measurements and the quality of communication between the agents. This introduces trade-offs between solutions that are compared using the concept of Pareto dominance. Multi-Objective Distributed Constraint Optimization Problems (MO-DCOPs) are used to model such problems where the goal is to find the set of Pareto optimal solutions. This set being exponential in the number of variables, it is important to consider fast approximation algorithms for MO-DCOPs. The bounded multi-objective max-sum (B-MOMS) algorithm is the first and only existing approximation algorithm for MO-DCOPs and is suited for solving a less-constrained problem. In this paper, we propose a novel approximation MO-DCOP algorithm called Distributed Pareto Local Search (DPLS) that uses a local search approach to find an approximation of the set of Pareto optimal solutions. DPLS provides a distributed version of an existing centralized algorithm by complying with the communication limitations and the privacy concerns of multi-agent systems. Experiments on a multi-objective extension of the graph-coloring problem show that DPLS finds significantly better solutions than B-MOMS for problems with medium to high constraint density while requiring a similar runtime.

Nonnegative Matrix Factorization (NMF) with sparseness and smoothness constraints has attracted increasing attention. When these properties are considered, NMF is usually formulated as an optimization problem in which a linear combination of an approximation error term and some regularization terms must be minimized under the constraint that the factor matrices are nonnegative. In this paper, we focus our attention on the error measure based on the Euclidean distance and propose a new iterative method for solving those optimization problems. The proposed method is based on the Hierarchical Alternating Least Squares (HALS) algorithm developed by Cichocki et al. We first present an example to show that the original HALS algorithm can increase the objective value. We then propose a new algorithm called the Gauss-Seidel HALS algorithm that decreases the objective value monotonically. We also prove that it has the global convergence property in the sense of Zangwill. We finally verify the effectiveness of the proposed algorithm through numerical experiments using synthetic and real data.

The purpose of this study is to investigate the effects of device size on non-visual icon search using a touch interface with voice output. We conducted an experiment in which twelve participants searched for the target icons with four different-sized touchscreen devices. We analyzed the search time, search strategies and subjective evaluations. As a result, mobile devices with a screen size of 4.7 inches had the shortest search time and obtained the highest subjective evaluation among the four devices.

Sponsored search is a mechanism that shows the appropriate advertisements (ads) according to search queries. The orders and payments of ads are determined by the auction. However, the externalities which give effects to CTR and haven't been considered in some existing works because the mechanism with externalities has high computational cost. In addition, some algorithms which can calculate the approximated solution considering the externalities within the polynomial-time are proposed, however, it assumed that one bidder can propose only a single ad. In this paper, we propose the approximation allocation algorithm that one bidder can offer many ads considering externalities. The proposed algorithm employs the concept of the combinatorial auction in order to consider the combinational bids. In addition, the proposed algorithm can find the approximated allocation by the dynamic programming. Moreover, we prove the computational complexity and the monotonicity of the proposed mechanism, and demonstrate computational costs and efficiency ratios by changing the number of ads, slots and maximum bids. The experimental results show that the proposed algorithm can calculate 0.7-approximation solution even though the full search can't find solutions in the limited times.

As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and -controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% compared to the conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

Internet of Things (IoT) devices deployed in urban areas are seen as data sources for urban sensing IoT applications. Since installing cellular interfaces on a huge number of IoT devices is expensive, we propose to use a user equipment (UE) device with a local wireless interface as a mobile IoT gateway for fixed IoT devices. In this paper, we design a new mobile architecture based on cellular networks to accommodate non-cellular fixed IoT devices by UE devices working as IoT gateways. One key feature is that our architecture leverages proximity services (ProSe) to discover relay UE devices with low overhead in terms of discovery messages. Through simulation studies, we clarify the feasibility of our architecture including the relay UE discovery mechanism in urban areas.

We demonstrate on the basis of ab initio calculations that metal-oxide-nitride-oxide-semiconductor (MONOS) memory is one of the most promising future high-density archive memories. We find that O related defects in a MONOS memory cause irreversible structural changes to the SiO2/Si3N4 interface at the atomistic level during program/erase (P/E) cycles. Carrier injection during the programming operation makes the structure energetically very stable, because all the O atoms in this structure take on three-fold-coordination. The estimated lifespan of the programmed state is of the order of a thousand years.

This paper presents a hierarchical-masked image filtering method for privacy-protection. Cameras are widely used for various applications, e.g., crime surveillance, environment monitoring, and marketing. However, invasion of privacy has become a serious social problem, especially regarding the use of surveillance cameras. Many surveillance cameras point at many people; thus, a large amount of our private information of our daily activities are under surveillance. However, several surveillance cameras currently on the market and related research often have a complicated or institutional masking privacy-protection functionality. To overcome this problem, a Hierarchical-Masked image Filtering (HMF) method is proposed, which has unmaskable (mask reversal) capability and is applicable to current surveillance camera systems for privacy-information protection and can satisfy privacy-protection related requirements. This method has five main features: unmasking of the original image from only the masked image and a cipher key, hierarchical-mask level control using parameters for the length of a pseudorandom number, robustness against malicious attackers, fast processing on an embedded processor, and applicability of mask operation to current surveillance camera systems. Previous studies have difficulty in providing these features. To evaluate HMF on actual equipment, an HMF-based prototype system is developed that mainly consists of a USB web camera, ultra-compact single board computer, and notebook PC. Through experiments, it is confirmed that the proposed method achieves mask level control and is robust against attacks. The increase in processing time of the HMF-based prototype system compared with a conventional non-masking system is only about 1.4%. This paper also reports on the comparison of the proposed method with conventional privacy protection methods and favorable responses of people toward the HMF-based prototype system both domestically and abroad. Therefore, the proposed HMF method can be applied to embedded systems such as those equipped with surveillance cameras for protecting privacy.

In this paper, we propose a similarity searchable encryption in the symmetric key setting for the weighted Euclidean distance, by extending the functional encryption scheme for inner product proposed by Bishop et al. [4]. Our scheme performs predetermined encoding independently of vectors x and y, and it obtains the weighted Euclidean distance between the two vectors while they remain encrypted.

The development of an extremely efficient packet inspection algorithm for lookup engines is important in order to realize high throughput and to lower energy dissipation. In this paper, we propose a new lookup engine based on a combination of a mismatch detection circuit and a linked-list hash table. The engine has an automatic rule registration and deletion function; the results are that it is only necessary to input rules, and the various tables included in the circuits, such as the Mismatch Table, Index Table, and Rule Table, will be automatically configured using the embedded hardware. This function utilizes a match/mismatch assessment for normal packet inspection operations. An experimental chip was fabricated using 40-nm 8-metal CMOS process technology. The chip operates at a frequency of 100MHz under a power supply voltage of VDD =1.1V. A throughput of 100Mpacket/s (=51.2Gb/s) is obtained at an operating frequency of 100MHz, which is three times greater than the throughput of 33Mpacket/s obtained with a conventional lookup engine without a mismatch detection circuit. The measured energy dissipation was a 1.58pJ/b·Search.

Smart education environment, that is a learning environment utilizing the Information Communication Technology (ICT), has attracted a great deal of attention. In order to expand this environment, we need a system that can establish the learning environment armed cloud systems to reduce a significant strain on teaching staff. The important issue for such system is extensibility because the system should be adapted to many kinds of original digital learning material with minimum modification. Therefore, this paper proposes “An Application Framework for Smart Education System: SES Framework”. In this Smart Education System, multi-aspect information concerning to a technical term embedded in the original digital learning material can be retrieved from different social media automatically. They can be also displayed on multi-screen devices according to user's operation. It is implemented based on “Transforming Model” which enables the migration of the original digital learning material to the smart education environment. It also has an easy operation flow for trainees named “three-step selection flow”. SES Framework derived from Model-View-Controller (MVC) pattern is based on the system architecture that enables triple mashup against the original digital learning material, external social media, and screen devices in front of users. All these functionalities have been implemented on cloud systems. We show SES Framework through the implementation example. We also demonstrate the effectiveness of SES Framework by indicating the system modification case study.

Delay Tolerant Networks (DTN) protocols based on the store-and-carry principle offer useful functions such as forwarding, utility value, social networks, and network coding. Although many DTN protocol proposals have been offered, work continues to improve performance. In order to implement DTN functions, each protocol introduces multiple parameters; their performance is largely dependent on how the parameter values are set. In this paper, we focus on improving spray and wait (S&W) by proposing a communication protocol named a Spray and AHP-GRA-based Forwarding (S&AGF) and Spray and Fuzzy based Forwarding (S&FF) scheme for DTN. The proposed protocols include a new forwarding scheme intended to extend network lifetime as well as maintain acceptable delivery ratio by addressing a deficiency in existing schemes that do not take energy into consideration. We choose the most suitable relay node by taking the energy, mobility, measured parameters of nodes into account. The simulation-based comparison demonstrates that the proposed S&AGF and S&FF schemes show better balanced performance level in terms of both delivery ratio and network lifetime than original S&W and its variants.

In the 5G era, centralized mobility management raises the issue of traffic concentration on the mobility anchor. Distributed mobility management is expected to be a solution for this issue, as it moves mobility anchor functions to multiple edge routers. However, it incurs path stretch and redundant traffic on the backhaul links. Although these issues were not considered important in the 3G/4G era, they are expected to be a serious problem in the 5G era. In this paper, we design a routing-based mobility management mechanism to address the above problems. The mechanism integrates distributed routing with Bloom Filters and an anchor-less scheme where edge routers work as mobility anchors. Simulations show that the proposed mechanism achieves a good balance between redundant traffic on the backhaul links and routing overhead.

In order to support seamless mobility in the Information-Centric Networking (ICN) Architecture we propose the Named-Node Network Architecture (3NA). 3NA introduces two independent namespaces to ICN, the 3N namespace used to uniquely identify nodes within a network and the Point of Attachment (PoA) namespace to identify a node's PoA to the network. The mappings between the two namespaces, along with all the necessary mechanisms to keep the mappings updated over time, are used when routing ICN packets to improve delay and the goodput when either the producer or the consumer are mobile. To support simultaneous producer and consumer mobility, we expand on the 3NA by adding a new Protocol Data Unit (PDU), the DU PDU. The DU PDU permits the encapsulation of ICN packets in a header that has source and destination name fields which belong to 3NA's 3N namespace. The new PDU permits seamless connectivity as long as 3NA's point of attachment signaling is strictly followed. We demonstrate the performance of the DU PDU against our previous defined communication methods and Named Data Networking's (NDN) Smart Flooding forwarding strategy using our open source nnnSIM module for the ns-3 framework. The new PDU outperforms all existing alternatives when the producer or both consumer and provider are mobile, obtaining overall lower mean network delay and higher median goodput.

Motif searching, i.e., identifying meaningful patterns from biological data, has been studied extensively due to its importance in the biomedical sciences. In this work, we seek to improve the performance of Weeder, a widely-used tool for automatic de novo motif searching. Weeder consists of several functions, among which we find that the function oligo_scan, which handles the pattern matching, is the bottleneck, especially when dealing with large datasets. Motivated by this observation, we adopt the Micron Automata Processor (AP) to accelerate the pattern-matching stage of Weeder. The AP is a massively-parallel, non-von-Neumann semiconductor architecture that is purpose-built for symbolic pattern matching. Relying on the fact that AP is capable of performing matching for thousands of patterns in parallel, we develop an AP-accelerated Weeder implementation in this work. In particular, we describe how to map Weeder's pattern matching to the AP chip and use the high-end FPGA on the AP board to postprocess the output from AP. Our experiment shows that the AP-accelerated Weeder achieves 751x speedup on pattern matching, compared to a single-threaded CPU implementation.