During the COVID-19 pandemic, a robust system for masked face recognition has been required. Most existing solutions used many samples per identity for the model to recognize, but the processes involved are very laborious in a real-life scenario. Therefore, we propose “CPNet” as a suitable and reliable way of recognizing masked faces from only a few samples per identity. The prototype classifier uses a few-shot learning paradigm to perform the recognition process. To handle complex and occluded facial features, we incorporated the covariance structure of the classes to refine the class distance calculation. We also used sharpness-aware minimization (SAM) to improve the classifier. Extensive in-depth experiments on a variety of datasets show that our method achieves remarkable results with accuracy as high as 95.3%, which is 3.4% higher than that of the baseline prototype network used for comparison.

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 µW.

This paper presents a 20GHz Class-C VCO using a noise sensitivity mitigation technique. A radio frequency Class-C VCO suffers from the AM-PM conversion, caused by the non-linear capacitance of cross coupled pair. In this paper, the phase noise degradation mechanism is discussed, and a desensitization technique of AM-PM noise is proposed. In the proposed technique, AM-PM sensitivity is canceled by tuning the tail impedance, which consists of 4-bit resistor switches. A 65-nm CMOS prototype of the proposed VCO demonstrates the oscillation frequency from 19.27 to 22.4GHz, and the phase noise of -105.7dBc/Hz at 1-MHz offset with the power dissipation of 6.84mW, which is equivalent to a Figure-of-Merit of -183.73dBc/Hz.

This paper presents a constant-current-controlled class-C VCO using a self-adjusting replica bias circuit. The proposed class-C VCO is more suitable in real-life applications as it can maintain constant current which is more robust in phase noise performance over variation of gate bias of cross-coupled pair comparing to a traditional approach without amplitude modulation issue. The proposed VCO is implemented in 180,nm CMOS process. It achieves a tuning range of 4.8--4.9,GHz with a phase noise of -121,dBc/Hz at 1,MHz offset. The power consumption of the core oscillators is 4.8,mW and an FoM of -189,dBc/Hz is achieved.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

Capacitive feedback VCOs use capacitors that are connected from the output node to the gate of the tail transistor that acts as a current source. Using such feedback results in modulating the current that is used by the oscillator and therefore changes its cyclostationary noise properties which results in a lower output phase noise. This paper presents a mathematical study of capacitive feedback VCOs in terms of stability and phase noise enhancement to confirm stability and to explain the enhancement in phase noise. The derived expression for the phase noise shows an improvement of 4.4 dB is achievable by using capacitive feedback as long as the VCO stays in the current limited region. Measurement results taken from an actual capacitive feedback VCO implemented in a 65 nm CMOS process also agrees with the analysis and simulation results which further validates the given analysis.

This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 µm CMOS technology, which oscillates at a carrier frequency of 4.5 GHz with a 0.2-V supply voltage. The measured phase noise is -104 dBc/Hz@1 MHz-offset with a power consumption of 114 µW, and the FoM is -187 dBc/Hz.

In a switched-capacitor (SC) circuit, the major block is an operational transconductance amplifier (OTA) designed in order to form a feedback loop. However, the OTA is the block that consumes most of the power in SC circuits. This paper proposes the use of a class-C inverter instead of the OTA in SC circuits and a corresponding switches configuration for extremely low power applications. A detailed analysis and design trade-offs are also provided. Simulation and experimental results show that sufficient performance can be obtained even though a class-C inverter is used. The second-order biquad filter and the second-order SC sigma-delta (ΣΔ) modulator based on a class-C inverter are designed. These circuits have been fabricated with a 0.35-µm CMOS process. The measurement results of the fabricated SC biquad filter show a 59-dB signal-to-noise-plus-distortion ratio (SNDR) for a 0.2-Vp-p input signal and 0.9-V dynamic ranges. The power consumption of the biquad filter is only 0.4 µW with a 1-V power supply. The measurement results of the fabricated ΣΔ modulator show a 61-dB peak SNR for a 1.6-kHz bandwidth with a sample rate of 200 kHz. The modulator consumes 0.8 µW with a 1-V power supply.