This study shows a fast simulation method of turbo codes over slow Rayleigh fading channels. The reduction of the simulation time is achieved by applying importance sampling (IS). The conventional IS method of turbo codes over Rayleigh fading channels focuses only on modification of additive white Gaussian noise (AWGN) sequences. The proposed IS method biases not only AWGNs but also channel gains of the Rayleigh fading channels. The computer runtime of the proposed method is about 1/5 of that of the conventional IS method on the evaluation of a frame error rate of 10-6. When we compare with the Monte Carlo simulation method, the proposed method needs only 1/100 simulation runtime under the condition of the same accuracy of the estimator.

In this paper, we derive a simple formula to generate a wide-sense systematic generator matrix(we call it quasi-systematic) B for a Reed-Solomon code. This formula can be utilized to construct an efficient interpolation based erasure-only decoder with time complexity O(n2) and space complexity O(n). Specifically, the decoding algorithm requires 3kr + r2 - 2r field additions, kr + r2 + r field negations, 2kr + r2 - r + k field multiplications and kr + r field inversions. Compared to another interpolation based erasure-only decoding algorithm derived by D.J.J. Versfeld et al., our algorithm is much more efficient for high-rate Reed-Solomon codes.

A simplified algorithm for check node processing of extended min-sum (EMS) q-ary LDPC decoders is presented in this letter. Compared with the bubble check algorithm, the so-called dynamic bubble-check (DBC) algorithm aims to further reduce the computational complexity for the elementary check node (ECN) processing. By introducing two flag vectors in ECN processing, The DBC algorithm can use the minimum number of comparisons at each step. Simulation results show that, DBC algorithm uses significantly fewer comparison operations than the bubble check algorithm, and presents no performance loss compared with standard EMS algorithm on AWGN channels.

Given an odd prime q and an integer m ≤ q, an array-based parity-check matrix H(m,q) can be constructed for a quasi-cyclic low-density parity-check (LDPC) code C(m,q). For m=4 and q ≥ 11, we prove the stopping distance of H(4,q) is 10, which is equal to the minimum Hamming distance of the associated code C(4,q). In addition, a tighter lower bound on the stopping distance of H(m,q) is also given for m > 4 and q ≥ 11.

In this letter, we use the the protograph low-density parity check (LDPC) codes to create bit-interleaved coded modulation (BICM) for the half-duplex decode-and-forward (DF) relay network. The DF relay BICM design problem can be transformed into a problem of rate-compatible BICM design, where the different segments of modulated symbols experience different signal-to-noise ratios (SNRs). To optimize the BICM based on the protograph structure, we use the protograph extrinsic information transfer (EXIT) to evaluate the thresholds of different mapping patterns between the variable nodes and the modulated bits. With this tool, we search for the most efficient mapping pattern of BICM for the half-duplex DF relay network. Our work can achieve significant gains over the existing work.

In the analysis of maximum-likelihood decoding performance of low-density parity-check (LDPC) codes, the weight distribution is an important factor. We presented a probabilistic method for computing the weight distribution of LDPC codes, and showed results of computing the weight distribution of several LDPC codes. In this paper, we improve our previously presented method and propose a probabilistic computation method with reliability for the weight distribution of LDPC codes. Using the proposed method, we can determine the weight distribution with small failure probability.

A new approach for encoding one class of quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. The proposed encoding method is applicable to parity-check matrices having dual-diagonal parity structure with single column of weight three in the parity generation region. Instead of finding the parity bits directly, the proposed method finds parity bits through vector correction. While the proposed LDPC encoding scheme is readily applicable to matrices defined in the IEEE physical layer standards, the computational complexity of the post processing operation for extraction of correction vector requires less effort than solving the linear equations involved with finding the parity bit as proposed by Myung et al.

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have several appealing properties regarding decoding, storage requirements and encoding aspects. In this paper, we focus on the QC LDPC codes over GF(q) whose parity-check matrices have fixed column weight j = 2. By investigating two subgraphs in the Tanner graphs of the corresponding base matrices, we derive two upper bounds on the minimum Hamming distance for this class of codes. In addition, a method is proposed to construct QC LDPC codes over GF(q), which have good Hamming distance distributions. Simulations show that our designed codes have good performance.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.

Irregular low-density parity-check (LDPC) codes generally have good decoding performance in the waterfall region, but they exhibit higher error floors than regular ones. In this letter, we present a hybrid method, which combines code construction and the iterative decoding algorithm, to tackle this problem. Simulation results show that the proposed scheme decreases the error floor significantly for irregular LDPC codes over binary-input additive white Gaussian noise (BIAWGN) channel.

An iterative inter-track interference (ITI) cancelling scheme is described for multi-track signal detection in nonbinary (NB)-LDPC-coded two-dimensional magnetic recording. The multi-track iterative ITI canceller that we propose consists of multi-track soft interference cancellers (SICs), two-dimensional partial response (TDPR) filters, noise-predictive max-log-MAP detectors, and an NB-LDPC decoder. TDPR filters using an ITI-suppressing tap-weight vector mitigate ITI in the first iteration. Multi-track SICs and TDPR filters adjusted to the residual two-dimensional ISI signals efficiently detect multi-track signals in the latter iterations. The simulation results demonstrated that our proposed iterative multi-track ITI canceller achieves frame error rates close to those obtained in a non-ITI case in media-noise-dominant environments when the both-side off-track ratio is up to 50%.

In this paper, we investigate the error floors of the non-binary low-density parity-check codes transmitted over the binary erasure channels under belief propagation decoding. We propose a method to improve the decoding erasure rates in the error floors by optimizing labels in zigzag cycles in the Tanner graphs of codes. Furthermore, we give lower bounds on the bit and the symbol erasure rates in the error floors. The simulation results show that the presented lower bounds are tight for the codes designed by the proposed method.

Over a correlated flat fading channel, multiple-symbol differential detection can enhance the performance of coded differential phase shift keying (DPSK) systems but with exponential complexity. For iterative decoding schemes, the soft-input soft-output (SISO) multiple-symbol differential sphere decoding (MSDSD) can offer suboptimal performance and its complexity is quadratic with detection length. To further reduce the complexity, this paper proposes a Forward/Backward MSDSD (FB-MSDSD) for coded DPSK systems. The key idea is that the detection interval is split into two subintervals which are processed in the forward and backward directions respectively. Simulation results show that the proposed scheme has almost the same performance and lower complexity when compared with the SISO-MSDSD scheme with the same detection length.

In this letter, we show that the code-trellis and the error-trellis for a convolutional code can be reduced simultaneously, if reduction is possible. Assume that the error-trellis can be reduced by shifting particular error-subsequences. In this case, if the identical shifts occur in the corresponding subsequences of each code-path, then the code-trellis can also be reduced. First, we obtain pairs of transformations which generate the identical shifts both in the subsequences of the code-path and in those of the error-path. Next, by applying these transformations to the generator matrix and the parity-check matrix, we show that reduction of these matrices is accomplished simultaneously, if it is possible. Moreover, it is shown that the two associated trellises are also reduced simultaneously.

The fixed points of the belief propagation decoder for non-binary low-density parity-check (LDPC) codes are referred to as stopping constellations. In this paper, we give the stopping constellation distributions for the irregular non-binary LDPC code ensembles defined over the general linear group. Moreover, we derive the exponential growth rate of the average stopping constellation distributions in the limit of large codelength.

We consider spatially-coupled protograph-based LDPC codes for the three terminal erasure relay channel. It is observed that BP threshold value, the maximal erasure probability of the channel for which decoding error probability converges to zero, of spatially-coupled codes, in particular spatially-coupled MacKay-Neal code, is close to the theoretical limit for the relay channel. Empirical results suggest that spatially-coupled protograph-based LDPC codes have great potential to achieve theoretical limit of a general relay channel.

Recently, Haley and Grant introduced the concept of reversible codes – a class of binary linear codes that can reuse the decoder architecture as the encoder and encodable by the iterative message-passing algorithm based on the Jacobi method over F2. They also developed a procedure to construct parity check matrices of a class of reversible codes named type-I reversible codes by utilizing properties specific to circulant matrices. In this paper, we refine a mathematical framework for reversible codes based on circulant matrices through a ring theoretic approach. This approach enables us to clarify the necessary and sufficient condition on which type-I reversible codes exist. Moreover, a systematic procedure to construct all circulant matrices that constitute parity check matrices of type-I reversible codes is also presented.

In this paper, we present a construction method of non-binary low-density parity-check (LDPC) convolutional codes. Our construction method is an extension of Felstrom and Zigangirov construction [1] for non-binary LDPC convolutional codes. The rate-compatibility of the non-binary convolutional code is also discussed. The proposed rate-compatible code is designed from one single mother (2,4)-regular non-binary LDPC convolutional code of rate 1/2. Higher-rate codes are produced by puncturing the mother code and lower-rate codes are produced by multiplicatively repeating the mother code. Simulation results show that non-binary LDPC convolutional codes of rate 1/2 outperform state-of-the-art binary LDPC convolutional codes with comparable constraint bit length. Also the derived low-rate and high-rate non-binary LDPC convolutional codes exhibit good decoding performance without loss of large gap to the Shannon limits.

Adaptive network coded cooperation (ANCC) scheme may have excellent performance for data transmission from a large collection of terminals to a common destination in wireless networks. However, the random relay selection strategy for ANCC protocol may generate the distributed low-density parity-check (LDPC) codes with many short cycles which may cause error floor and performance degradation. In this paper, an optimized relay selection strategy for ANCC is proposed. Before data communication, by exploiting low-cost information interaction between the destination and terminals, the proposed method generates good assembles of distributed LDPC codes and its storage requirement reduces dramatically. Simulation results demonstrate that the proposed relay selection protocol significantly outperforms the random relay selection strategy.