The Mobius cube MQn proposed by Cull et al. is an alternative to the popular hypercube network. Recently, MQn was shown to be pancyclic, i.e., cycles of any lengths at least four can be embedded into it. Due to the importance of the fault tolerance in the parallel processing area, in this paper, we study an injured MQn with mixed node and link faults. We show that it is (n - 2)-fault-tolerant pancyclic for n 3, that is, an injured n-dimensional MQn is still pancyclic with up to (n - 2) faults. Furthermore, our result is optimal.

A UPS with an energy storage function using long-cycle-life VRLA batteries has been developed. Combining the functions of UPS and energy storage is effective to enhance the cost-effectiveness of the UPS. New long-cycle-life VRLA batteries, with capacities of 1000 or 1500 Ah at 2 V, have been developed for the UPS. A cycle life of 3000 or more cycles was estimated from our cycle test. The UPS has been installed in a telecommunications building for field-testing. This paper describes the system configuration, electrical characteristics of the UPS and its components, and result of our field test.

Through many researches on modeling and analyzing biological pathways, Petri net has recognized as a promising method for representing biological pathways. Recently, Matsuno et al. (2003) introduced hybrid functional Petri net (HFPN) for giving more intuitive and natural biological pathway modeling method than existing Petri nets. They also developed Genomic Object Net (GON) which employs the HFPN as a basic architecture. Many kinds of biological pathways have been modeled with the HFPN and simulated by the GON. This paper gives a new HFPN model of "cell cycle of fission yeast" with giving six basic HFPN components of typical biological reactions, and demonstrating the method how biological pathways can be modeled with these HFPN components. Simulation results by GON suggest a new hypothesis which will help biologist for performing further experiments.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

In December 2001, the authors started two kinds of experiments on the meteor burst communication (MBC) in Antarctica to study the ability of MBC as a communication medium for data collection systems in that region. In the first experiment, a continuous tone signal is transmitted from Zhongshan Station. The signal received at Syowa Station (about 1,400 km apart) is recorded and analyzed. This experiment is aimed to study basic properties of the meteor burst channel in that high latitude region. On the other hand, the second experiment is designed to estimate data throughput of a commercial MBC system in that region. A remote station at Zhongshan Station tries to transfer data packets each consisting of 10 data words to the master station at Syowa Station. Data packets are generated with five minutes interval. In this paper, we explain the experiments, briefly examine the results of the first year (from April 2002 to March 2003), and put forward the plan for the experiments in the second and third year. From the data available thus far, we can see that 1) the sinusoidal daily variation in the meteor activity typical in middle and low latitude regions can not be clearly seen, 2) non-meteoric propagations frequently dominate the channel especially during night hours, 3) about 60% of the generated data packets are successfully transferred to the master station within two hours delay even though we are now operating the data transfer system only for five minutes in each ten minutes interval, etc.

In policy-based management, in addition to deliver and enforce policies in managed systems, it is inevitable to manage the policy life-cycle. We mean the policy life-cycle as cyclic iteration of processes involving monitoring to see if the enforced policies actually work at operators' will and their adaptation based on monitoring. Enabling such policy life-cycle management by the current centralized management paradigm such as SNMP may, however, result in poor scalability and reliability. This is typically due to much bandwidth consumption for monitoring and communication failure between a management system and a managed system. It may also impose a heavy burden on the operators in analyzing management information for the policy adaptation. For a solution to that, we propose a scalable and reliable policy-based management scheme enabling the policy life-cycle management based on distributed management paradigm. In the scheme, we provide a new management script describing policies and how their life-cycle should be managed, and execute the script on the managed system with enough computation resources. The scheme can make the current policy-based management more scalable by reducing management traffic, more reliable by distributing management tasks to the managed systems, and more promising by relieving of the operators' burden. We implement a prototype system based on the scheme taking Differentiated Services as a policy enforcement mechanism, and evaluate the scheme from the following viewpoints: 1) the reliability, 2) relievability, and 3) scalability. The first two will be shown with a policy adaptation scenario in an operational network. The last one will be investigated in terms of the management traffic reduction by a management script, the management traffic required for the management of a management script, and the load on a managed system to execute management scripts. As deployment consideration of the proposed scheme besides technical aspects, we also discuss how the prototype system could be integrated with managed systems compliant to the standards emerging in the marketplace.

Evaluation of cyclic transitions in the discrete-time neural networks with antisymmetric and circular interconnection weights has been derived in an asymptotic mathematical form. The type and the number of limit cycles generated by circular networks, in which each neuron is connected only to its nearest neurons, have been investigated through analytical method. The results show that the estimated numbers of state vectors generating n- or 2n-periodic limit cycles are an exponential function of (1.6)n for a large number of neuron, n. The sufficient conditions for state vectors to generate limit cycles of period n or 2n are also given.

H-coloring problem is a coloring problem with restrictions such that some pairs of colors cannot be used for adjacent vertices, where H is a graph representing the restrictions of colors. We deal with the case that H is the complement graph of a cycle of odd order 2p + 1. This paper presents the following results: (1) chordal graphs and internally maximal planar graphs are -colorable if and only if they are p-colorable (p 2), (2) -coloring problem on planar graphs is NP-complete, and (3) there exists a class that includes infinitely many -colorable but non-3-colorable planar graphs.

In this paper, we propose a synthesis method of hybrid systems with specified limit cycles. Several methods which sysnthesize a nonlinear system with prescribed limit cycles have been proposed. In these methods, the limit cycle is given by an algebraic equation, which will be called constraint equations, and its stability is guaranteed by a Lyapunov function derived from the constraint equation. In general, limit cycles of hybrid systems are nonsmooth due to the discontinuous vector fields. So the limit cycles are given by piecewise smooth constraint equations, we employ the piecewise smooth Lyapunov functions to construct desired nonsmooth limit cycles and guarantee their stability.

A novel modified midtread quantizer is proposed for number-controlled oscillator frequency quantization in digital phase-locked loops (DPLLs). We show that DPLLs employing the proposed quantizer provide significantly improved cycle slip performance compared to those employing conventional midtread or midrise quantizers, especially when the number of quantization bits is small and the magnitude of input signal frequency normalized by the quantization interval is less than 0.5.

This paper proposes a fast multi-cycle path detection method for large sequential circuits. The proposed method is based on ATPG techniques, especially on implication techniques, to use circuit structures and multi-cycle path conditions directly. The method also checks whether or not a multi-cycle path may be invalidated by static hazards at the inputs of flip-flops. Then we explain how to apply the proposed algorithm to real industrial designs. Experimental results show that our method is much faster than conventional ones and that it is efficient enough to handle large industrial designs.

We propose a new effective method of managing flash memory space for flash memory-specific file systems based on a log-structured file system. Flash memory has attractive features such as non-volatility and fast I/O speed, but it also suffers from inability to update in situ and from limited usage (erase) cycles. These drawbacks necessitate a number of changes to conventional storage (file) management techniques. Our focus is on lowering cleaning cost and evenly utilizing flash memory cells while maintaining a balance between these two often-conflicting goals. The proposed cleaning method performs well especially when storage utilization and the degree of locality are high. The cleaning efficiency is enhanced by dynamically separating cold data and non-cold data, which is called 'collection operation.' The second goal, that of cycle-leveling, is achieved to the degree that the maximum difference between erase cycles is below the error range of the hardware. Experimental results show that the proposed technique provides sufficient performance for reliable flash storage systems.

This paper considers a software reliability model which allows for two types of imperfect debuggings at each failure of the software system. For one type of imperfect debugging, a fault that causes the failure is imperfectly debugged without altering the fault contents of the software system. For the other type of imperfect debugging, the fault is not only imperfectly debugged, but also a new fault is generated and introduced into the system. The probability of perfect debugging is assumed to be an increasing function of the number of debuggings performed prior to the current failure of the system. Based on the software reliability model presented, we consider three profit models to determine the optimal software release times which maximize the expected software profit. These models consider: (1) constant life cycle, (2) random life cycle, (3) random life cycle and penalty cost which is imposed when the software is delivered late. The optimal release times are shown to be finite and unique. Numerical examples are provided for illustrative purposes.

We have designed a 32-bit RISC microprocessor with 16-/32-bit fixed-point DSP functionality. This processor, called YD-RISC, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline structure. The pipelined DSP unit can execute one 32-bit multiply-accumulate (MAC) or 16-bit complex multiply instruction every one or two cycles through two 17-b 17-b multipliers and an operand examination logic circuit. Power-saving techniques such as power-down mode and disabling execution blocks allow low power consumption. In the design of this processor, we use logic synthesis and automatic place-and-route. This top-down approach shortens design time, while a high clock frequency is achieved by refining the processor architecture.

In this report, a design method of neural networks for limit cycle generator is described. First, the constraint conditions for the synaptic weights, which are given by the linear inequalities, are derived from the dynamics of neural networks. Next, the linear inequalities are solved by the linear programming method. The synaptic weights and other parameters are determined by the above solutions. Furthermore, neuro-based limit cycle generator is designed with analog electronic circuits and simulated by Spice. Finally, we confirm that our design method is efficient and practical for the design of neuro-based limit cycle generator.

This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

In this paper, we propose the majority algorithm to choose the connection weights for the neural networks with quantized connection weights of 1 and 0. We also obtained the layered network to solve the parity problem with the input of arbitrary number N through an application of this algorithm. The network can be expected to have the same ability of generalization as the network trained with learning rules. This is because it is possible to decide the connection weights, regardless of the size of the training set. One can decide connection weights without learning according to our case study. Thus, we expect that the proposed algorithm may be applied for a real-time processing.

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.

A novel combinatorial optimization algorithm called "Gradual neural network (GNN)" is presented for NP-complete broadcast scheduling problems in packet radio (PR) networks. A PR network provides data communications services to a set of geographically distributed nodes through a common radio channel. A time division multiple access (TDMA) protocol is adopted for conflict-free communications, where packets are transmitted in repetition of fixed-length time-slots called a TDMA cycle. Given a PR network, the goal of GNN is to find a TDMA cycle with the minimum delay time for each node to broadcast packets. GNN for the N-node-M-slot TDMA cycle problem consists of a neural network with N M binary neurons and a gradual expansion scheme. The neural network not only satisfies the constraints but also maximizes transmissions by two energy functions, whereas the gradual expansion scheme minimizes the cycle length by gradually expanding the size of the neural network. The performance is evaluated through extensive simulations in benchmark instances and in geometric graph instances with up to 1000 vertices, where GNN always finds better TDMA cycles than existing algorithms. The result in this paper supports the credibility of our GNN algorithm for a class of combinatorial optimization problems.