In this paper, we propose a method for enhancing performance of a sequential version of the belief-propagation (BP) decoding algorithm, the group shuffled BP decoding algorithm for low-density parity-check (LDPC) codes. An improved BP decoding algorithm, called the shuffled BP decoding algorithm, decodes each symbol node in serial at each iteration. To reduce the decoding delay of the shuffled BP decoding algorithm, the group shuffled BP decoding algorithm divides all symbol nodes into several groups. In contrast to the original group shuffled BP, which automatically generates groups according to symbol positions, in this paper we propose a method for grouping symbol nodes which generates groups according to the structure of a Tanner graph of the codes. The proposed method can accelerate the convergence of the group shuffled BP algorithm and obtain a lower error rate in a small number of iterations. We show by simulation results that the decoding performance of the proposed method is improved compared with those of the shuffled BP decoding algorithm and the group shuffled BP decoding algorithm.

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back- interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the "medium-thickness" poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back- threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front- gate biases. We evaluated the front- and back- interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back- interface trap densities for both samples in initial state are around 51011 to 1.31012 cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

A useful optimization problem to help solve various base station layout problems in multihop wireless networks is formulated. By solving the proposed generalized formula, the relation between the permissible largest number of hops and the minimum base station density necessary to cover an entire service area while guaranteeing a specified QoS is easily calculated. Our formula is extendable to other allocation problems by replacing parameters. The energy-cost transformation and scope of the multihop effect are also presented.

This paper reports the new gate and recess structure design of millimeter-wave, high power pHEMTs, which highly improves humidity resistance and reliability. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, strong moisture resistance was obtained without degradation of the device characteristics. Moreover, we have designed a stepped recess structure to increase the on-state breakdown voltage without degradation of the power density of the millimeter-wave pHEMT, according to the analysis based on the new nonlinear drain resistance model. Consequently, the developed pHEMT has shown strong humidity resistance with no degradation of the DC characteristics even after 1000 hours storage at 400 K and 85% humidity, and the high on-state breakdown voltage of over 30 V while keeping the high power density of 0.65 W/mm in the Ka band. In addition, the proposed nonlinear drain resistance model effectively explains this power performance.

Bone Mineral Density (BMD) is an indicator of osteoporosis that is an increasingly serious disease, particularly for the elderly. To calculate BMD, we need to measure the volume of the femur in a noninvasive way. In this paper, we propose a noninvasive bone volume measurement method using x-ray attenuation on radiography and medical knowledge. The absolute thickness at one reference pixel and the relative thickness at all pixels of the bone in the x-ray image are used to calculate the volume and the BMD. First, the absolute bone thickness of one particular pixel is estimated by the known geometric shape of a specific bone part as medical knowledge. The relative bone thicknesses of all pixels are then calculated by x-ray attenuation of each pixel. Finally, given the absolute bone thickness of the reference pixel, the absolute bone thickness of all pixels is mapped. To evaluate the performance of the proposed method, experiments on 300 subjects were performed. We found that the method provides good estimations of real BMD values of femur bone. Estimates shows a high linear correlation of 0.96 between the volume Bone Mineral Density (vBMD) of CT-SCAN and computed vBMD (all P<0.001). The BMD results reveal 3.23% difference in volume from the BMD of CT-SCAN.

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

In this letter, we present quasi-Jacket block matrices over GF(2), i.e., binary matrices which all are belong to a class of cocyclic matrices. These matrices are may be useful in digital signal processing, CDMA, and coded modulation. Based on Circular Permutation Matrix (CPM) cocyclic quasi-Jacket block low-density matrix is introduced in this letter which is useful in coding theory. Additionally, we show that the fast algorithm of quasi-Jacket block matrix.

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.

Due to the limited resources of sensor nodes, an energy-efficient routing algorithm of Wireless Sensor Networks is considered as one of the most important issues in improving network lifetime. To resolve this issue, several routing algorithms have been suggested, but the published studies have mainly focused on minimizing distances between sensor nodes or the number of hops. These researches have also assumed that all the sensor nodes participate in the sensing task. In this paper, we propose a new cluster head selection algorithm focusing on both the density of sensor nodes and sensing-awareness that has not been considered yet in other existing researches on cluster-based routing scheme. In the real sensor network environment, only a part of sensor nodes participates in data reporting, so consideration of sensing-awareness in a routing algorithm will have effect on network efficiency. Moreover, the density of sensor nodes that has resulted from geographical location of sensor nodes can be an important factor in cluster head selection. The simulation results show that the proposed algorithm, by considering these 2 factors simultaneously, reduces energy consumption and enhances network lifetime.

In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

In this paper, we derive an upper bound for the average block error probability of a standard irregular low-density parity-check (LDPC) code ensemble under the maximum-likelihood (ML) decoding. Moreover, we show that the upper bound asymptotically decreases polynomially with the code length. Furthermore, when we consider several regular LDPC code ensembles as special cases of standard irregular ones over an additive white Gaussian noise channel, we numerically show that the signal-to-noise ratio (SNR) thresholds at which the proposed bound converges to zero as the code length tends to infinity are smaller than those for a bound provided by Miller et al.. We also give an example of a standard irregular LDPC code ensemble which has a lower SNR threshold than a given regular LDPC code ensemble.

In this letter, we propose a new modification to the belief propagation (BP) decoding algorithm for Finite-Geometry low-density parity-check (LDPC) codes. The modification is based on introducing feedback into the iterative process, which can break the oscillations of bit log-likelihood ratio (LLR) values. Simulations show that, with a given maximum iteration, the "feedback BP" (FBP) algorithm can achieve better performance than the conventional belief propagation algorithm.

Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves approximate Maximum Likelihood (ML) decoding. ML decoding is effective to lower error floors. However, the OSD estimates satisfy the parity check equation of the LDPC code even the estimates are wrong. Hybrid decoder combining LLR-BP decoding algorithm and the OSD algorithm cannot also lower error floors, because wrong estimates also satisfy the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Owing to CRC, we can detect wrong codewords from OSD estimates. Our CRC-LDPC code with hybrid decoder can lower error floors in an AWGN channel. In wireless communications, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit. In this paper, we evaluate the Block Error Rate (BLER) of the CRC-LDPC code with hybrid decoder in a fast fading channel with perfect and imperfect CSIs where 'imperfect CSI' means that the distribution of channel and those statistical average of the fading amplitudes are known at the receiver. By computer simulation, we show that the CRC-LDPC code with hybrid decoder can lower error floors than the conventional LDPC code with hybrid decoder in the fast fading channel with perfect and imperfect CSIs. We also show that combining error detection with the OSD algorithm is effective not only for lowering the error floor but also for reducing computational complexity of the OSD algorithm.

Decoding performance of LDPC (Low-Density Parity-Check) codes is highly dependent on the degree distributions of the Tanner graphs which define the LDPC codes. We compare two LDPC code ensembles, one has a uniform degree distribution and the other a non-uniform one over a BEC (Binary Erasure Channel) and a BSC (Binary Symmetric Channel) thorough DE (Density Evolution). We then derive sufficient conditions on the erasure probability of a BEC and the error probability of a BSC, under which the LDPC code ensembles with uniform degree distributions outperform those with non-uniform degree distributions.

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [µm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

Recently, a word-valued source has been proposed as a new class of information source models. A word-valued source is regarded as a source with a probability distribution over a word set. Although a word-valued source is a nonstationary source in general, it has been proved that an entropy rate of the source exists and the Asymptotic Equipartition Property (AEP) holds when the word set of the source is prefix-free. However, when the word set is not prefix-free (non-prefix-free), only an upper bound on the entropy density rate for an i.i.d. word-valued source has been derived so far. In this paper, we newly derive a lower bound on the entropy density rate for an i.i.d. word-valued source with a finite non-prefix-free word set. Then some numerical examples are given in order to investigate the behavior of the bounds.

Irregular Repeat-Accumulate (IRA) codes, introduced by Jin et al., have a linear-time encoding algorithm and their decoding performance is comparable to that of irregular low-density parity-check (LDPC) codes. Meanwhile the authors have introduced detailedly represented irregular LDPC code ensembles specified with joint degree distributions between variable nodes and check nodes. In this paper, by using density evolution method [7],[8], we optimize IRA codes specified with joint degree distributions. Resulting codes have higher thresholds than Jin's IRA codes.

If the signal is not Gaussian, then the power spectral density (PSD) approach is insufficient to analyze signals and we resort to estimate the higher order spectra of the signal. However, estimation of the higher order spectra is even more time consuming, for example, the complexity of trispectrum is O(N 4). This problem becomes even more serious when short time Fourier transform (STFT) is computed - computation of the trispectrum is required after every shift of the window. In this paper, a method to recursively compute trispectrum has been presented and it is shown that the computational complexity, for a window size of N, is reduced to be O(N 3) and is the same as the space complexity.

We study a modification method for constructing low-density parity-check (LDPC) codes for solid burst erasures. Our proposed modification method is based on a column permutation technique for a parity-check matrix of the original LDPC codes. It can change the burst erasure correction capabilities without degradation in the performance over random erasure channels. We show by simulation results that the performance of codes permuted by our method are better than that of the original codes, especially with two or more solid burst erasures.

Multi-Edge type Low-Density Parity-Check codes (MET-LDPC codes) introduced by Richardson and Urbanke are generalized LDPC codes which can be seen as LDPC codes obtained by concatenating several standard (ir)regular LDPC codes. We prove in this paper that MET-LDPC code ensembles possess a certain symmetry with respect to their Average Coset Weight Distributions (ACWD). Using this symmetry, we drive ACWD of MET-LDPC code ensembles from ACWD of their constituent ensembles.