In this paper, we propose an algorithm to calculate the higher moments of the busy period length of a discrete-time M/G/1 type queue with finite buffer. The queueing model has a level-dependent transition probability matrix. Our algorithm is given as a set of recursive formulas which are derived from the relationship among the generating function matrices of the fundamental period. As an example of our algorithm, we provide an approximate analysis of a HOL (Head Of Line) priority control queue.

In this paper, a discrete-time convergence theorem for continuous-state Hopfield networks with self-interaction neurons is proposed. This theorem differs from the previous work by Wang in that the original updating rule is maintained while the network is still guaranteed to monotonically decrease to a stable state. The relationship between the parameters in a typical class of energy functions is also investigated, and consequently a "guided trial-and-error" technique is proposed to determine the parameter values. The third problem discussed in this paper is the post-processing of outputs, which turns out to be rather important even though it never attracts enough attention. The effectiveness of all the theorems and post-processing methods proposed in this paper is demonstrated by a large number of computer simulations on the assignment problem and the N-queen problem of different sizes.

This paper proposes a measure of coefficient quantization errors for linear discrete-time state-space systems. The proposed measure of state-space systems agrees with the actual output error variance since it is derived from the exact evaluation of the output error variance due to coefficient deviation. The measure in this paper is represented by the controllability and the observability gramians and the state covariance matrix of the system. When the variance of coefficient variations is very small, the proposed measure is identical to the conventional statistical sensitivity of state-space systems. This paper also proposes a method of synthesizing minimum measure structures. Numerical examples show that the proposed measure is in very good agreement with the actual output error variance, and that minimum measure structures have a very small degradation of the frequency characteristic due to coefficient quantization.

This paper provides a new robust guaranteed cost controller design method for discrete parameter uncertain time delay systems. The result shows much tighter bound of guaranteed cost than that of existing paper. In order to get the optimal (minimum) value of guaranteed cost, an optimization problem is given by linear matrix inequality (LMI) technique. Also, the parameter uncertain systems with time delays in both state and control input are considered.

Wireless LANs have been used for realizing fully-distributed users in a multimedia environment that has the ability to provide real-time bursty traffic (such as voice or video) and data traffic. In this paper, we present a new realistic and detailed system model and a new effective analysis for the performance of wireless LANs which support multimedia communication with non-persistent carrier sense multiple access with collision avoidance (CSMA/CA) protocol. In this CSMA/CA model, a user with a packet ready to transmit initially sends some pulse signals with random intervals within a collision avoidance period before transmitting the packet to verify a clear channel. The system model consists of a finite number of users to efficiently share a common channel. Each user can be a source of both voice traffic and data traffic. The time axis is slotted, and a frame has a large number of slots and includes two parts: the collision avoidance period and the packet transmission period. A discrete-time Markov process is used to model the system operation. The number of slots in a frame can be arbitrary, dependent on the chosen lengths of the collision avoidance period and packet transmission period. Numerical results are shown in terms of channel utilization and average packet delay for different packet generation rates. They indicate that the network performance can be improved by adequate choice of ratios between the collision avoidance period and transmission period, and the pulse transmission probability.

In this paper, a novel chaos circuit with long working-life is proposed. The proposed circuit consists of NMOS-coupled discrete-time chaotic cell circuits. By employing chaos synchronization phenomenon, the proposed circuit can achieve long working-life. Since the proposed circuit is less susceptible to breakdown, the rate of the acceptable product for chaos IC can be improved. Furthermore, thanks to the coupling by using NMOSFET's, the loss of the connection line between chaotic cell circuits can be controlled electronically. Therefore, the proposed system designed by using switched-current (SI) techniques is useful as an experimental tool to analyze chaos synchronization phenomena. The validity of the proposed circuits is confirmed by computer simulations and experiments.

In this letter, a simple design of a discrete-time chaos circuit realizing a tent map is proposed. The proposed circuit can be constructed with 13 MOSFET's and 2 capacitors. Concerning the proposed circuit synthesized using switched-current (SI) techniques, the validity of the circuit design is analyzed by SPICE simulations. Furthermore, the proposed circuit is built with commercially-available IC's. The proposed circuit is integrable by a standard CMOS technology.

The robust induced l-norm control problem is considered for uncertain discrete-time systems. We propose a state feedback and an output feedback controller that quadratically stabilize the systems and satisfy a given constraint on the induced l-norm. Both controllers are constructed by solving a set of scalar-dependent linear matrix inequalities (LMI's), and the gain matrices are characterized by the solution to the LMI's.

This paper proposes a new design method of nonlinear filtering and fixed-point smoothing algorithms in discrete-time stochastic systems. The observed value consists of nonlinearly modulated signal and additive white Gaussian observation noise. The filtering and fixed-point smoothing algorithms are designed based on the same idea as the extended Kalman filter derived based on the recursive least-squares Kalman filter in linear discrete-time stochastic systems. The proposed filter and fixed-point smoother necessitate the information of the autocovariance function of the signal, the variance of the observation noise, the nonlinear observation function and its differentiated one with respect to the signal. The estimation accuracy of the proposed extended filter is compared with the extended maximum a posteriori (MAP) filter theoretically. Also, the current estimators are compared in estimation accuracy with the extended MAP estimators, the extended Kalman estimators and the Kalman neuro computing method numerically.

In this paper, a new digital chaos circuit which can generate multiple-scroll strange attractors is proposed. Being based on the piecewise-linear function which is determined by on-chip supervised learning, the proposed digital chaos circuit can generate multiple-scroll strange attractors. Hence, the proposed circuit can exhibit various bifurcation phenomena. By numerical simulations, the learning dynamics and the quasi-chaos generation of the proposed digital chaos circuit are analyzed in detail. Furthermore, as a design example of the integrated digital chaos circuit, the proposed circuit realizing the nonlinear function with five breakpoints is implemented onto the FPGA (Field Programmable Gate Array). The synthesized FPGA circuit which can generate n-scroll strange attractors (n=1, 2, 4) showed that the proposed circuit is implementable onto a single FPGA except for the SRAM.

In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.

In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.

An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).

In this Letter, we investigate the loss performance of a discrete-time single-server queueing system with periodic vacations, with which we are often confronted in traffic control, such as cell scheduling or priority control schemes, at ATM nodes. Explicit expressions are derived for the cell loss ratio in terms of the distribution of the buffer contents in an infinite capacity queue.

A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

We present a minimal lattice realization of MIMO linear discrete-time systems which interpolate the desired Markov and covariance parameters. The minimal lattice realization is derived via a recursive construction algorithm based on the state space description and it parametrizes all the interpolants.

Discrete-time chaotic circuits realizing a tent map and a Bernoulli map are synthesized using switched-current (SI) techniques. For these proposed circuits, simulations are performed concerning the return maps and bifurcation trees. The theoretical analysis is carried out to predict the bifurcation tree under the existence of the nonidealities in the return map. This analysis has been done by assuming the return maps to be piecewise linear. The proposed circuits are built with commerciallyavailable IC's. And their return maps and bifurcation trees are measured in the experiment. The design formulas are obtained for the bifurcation trees and they are confirmed by the simulation results. The proposed circuits are integrable by a standard BiCMOS technology.

In this study, we discuss a discrete-time cellular neural network (DTCNN) and its applications including convergence property and stability. Two theorems about the convergence condition of nonreciprocal non-uniform DTCNNs are described, which cover those of reciprocal one as a special case. Thus, it can be applied to wide classes of image processings, such as associative memories, multiple visual patterns recognition and others. Our DTCNN realized by the software simulation can largely reduce the computational time compared to the continuous-time CNN.

We present a recursive algorithm for constructing linear discrete-time systems which interpolate the desired 1st-and 2nd-order information. The recursive algorithm constructs a new system and connects it to the previous system in the cascade form every time new information is added. These procedures yield a practical realization of all the interpolants.