Two voltage controlled current source (VCCS) models of double-channel p-type lateral extended drain MOS (DPLEDMOS) are firstly proposed to analyze the energy recovery circuit (ERC) efficiency of PDP data driver IC. In terms of the mathematical function between ID and VDS, the VCCS models are created. The presented models can be embedded in system software Saber to simulate the ERC waveform of data driver IC. A test board and a PDP system are used to verify the accuracy of the VCCS models. The experimental measurements agree with the simulation results very well and the maximum model error is 3.89%. Simulation results also show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time TERC, the drain current ID, and the capacitance of CL. In an actual PDP system, TERC is restricted and CL is changeless. The ERC efficiency of PDP data driver IC can be improved significantly by using DPLEDMOS which has higher ID capacity. The proposed VCCS models of DPLEDMOS can be used to predict the ERC efficiency accurately.

A compact (13.38.05.6 mm) 40 Gbit/s 1.55-µm electroabsorption (EA) modulator monolithically integrated distributed feedback (DFB) laser diode (EML) [1] module integrated with a driver IC has been developed. Its compactness was realized by employing a broadband feed-through and a bias tee which were accurately designed by 3-dimensional (3D) electromagnetic simulation. It was confirmed that the simulation results of the frequency response and the actual measurement results are corresponding well. Clear eye opening of the 40 Gbit/s optical output waveform of the fabricated EML module was observed. Degradation was not observed even when the 40 Gbit/s electrical signal was launched into the module via the flexible printed circuit (FPC).

It is very difficult to simultaneously achieve power and cost reductions in address-driver circuits of a plasma-display panel (PDP) unit in which an energy-recovery scheme utilizing the resonance of a series-connected inductor and electrode parasitic capacitors is used. This is because an increase in parasitic capacitance and high-speed circuit operation become necessary as the display panel becomes larger in size and higher in resolution. In particular, low-power operation of address-driver ICs is key to avoiding the installation of heat sinks on the ICs. We propose herein new power-dispersion methods that can greatly reduce the power dissipation of address-driver ICs even when large parasitic capacitance is driven at high speed. The proposed methods enable a reduction in the power dissipation of address-driver ICs without deteriorating the operational speed by dispersing their powers into external resistors, and by supplying power to address-driver ICs in two voltage steps during both rising and falling time intervals when the address changes. Our results indicate that the power dissipation of address-driver ICs and the total cost of the address drive unit of a plasma-display panel can be reduced to 29% and 53%, respectively, compared with those of the ICs and the unit that are driven by the conventional address-driving method.

In this letter, we propose new driving methods for designing a driver independent of the current property of Organic Light Emitting Diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. In particular, the proposed methods are used for the manufacturing of 1.8" 128 128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6 µm, 2-poly, 3-metal CMOS process and applied to the Personal Communication System (PCS) phone successfully.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.