The probability of making mistakes on the decoded signals at the relay has been used for the maximum-likelihood (ML) decision at the receiver in the decode-and-forward (DF) relay network. It is well known that deriving the probability is relatively easy for the uncoded single-antenna transmission with M-pulse amplitude modulation (PAM). However, in the multiplexing multiple-input multiple-output (MIMO) transmission, the multi-dimensional decision region is getting too complicated to derive the probability. In this paper, a high-performance near-ML decoder is devised by applying a well-known pairwise error probability (PEP) of two paired-signals at the relay in the MIMO DF relay network. It also proves that the near-ML decoder can achieve the maximum diversity of MSMD+MR min (MS,MD), where MS, MR, and MD are the number of antennas at the source, relay, and destination, respectively. The simulation results show that 1) the near-ML decoder achieves the diversity we derived and 2) the bit error probability of the near-ML decoder is almost the same as that of the ML decoder.

We consider a model composed of nonlinear perceptrons and analytically investigate its generalization performance using correlated examples in the framework of on-line learning by a statistical mechanical method. In Hebbian and AdaTron learning, the larger the number of examples used in an update, the slower the learning. In contrast, Perceptron learning does not exhibit such behaviors, and the learning becomes fast in some time region.

Weight perturbation learning was proposed as a learning rule in which perturbation is added to the variable parameters of learning machines. The generalization performance of weight perturbation learning was analyzed by statistical mechanical methods and was found to have the same asymptotic generalization property as perceptron learning. In this paper we consider the difference between perceptron learning and AdaTron learning, both of which are well-known learning rules. By applying this difference to weight perturbation learning, we propose adaptive weight perturbation learning. The generalization performance of the proposed rule is analyzed by statistical mechanical methods, and it is shown that the proposed learning rule has an outstanding asymptotic property equivalent to that of AdaTron learning.

This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.

In this letter, we analyze the amplify-and-forward (AF) two-way cooperative relaying scheme with regard to the average data transmission rate and the symbol error probability. By investigating the Moment-Generating function (MGF) and the k-th moment of “extra-harmonic” mean of two variables, we derive an exact closed-form expression for the symbol error probability (SEP) and the approximate average sum rate. Analysis results show that the proposed scheme achieves higher SEP performance as well as a lower data rate than the conventional AF two-way scheme. Additionally, it also matches the SEP performance of the one-way AF cooperative scheme but attains higher sum rate. Finally, Monte Carlo simulation results will be shown to confirm our analytical results.

Some statistical characteristics, including the means and the cross-correlations, of frequency-selective Rician fading channels seen by orthogonal frequency division multiplexing (OFDM) subcarriers are derived in this paper. Based on a pairwise error probability analysis, the mean vector and the cross-correlation matrix are used to obtain an upper bound of the overall bit-error rate (BER) in a closed-form for coded OFDM signals with and without inter-carrier interference. In this paper, the overall BER is defined as the average BER of OFDM signals of all subcarriers obtained by considering their cross-correlations. Numerical examples are presented to compare the proposed upper bound of the overall BERs and the overall BERs obtained by simulations.

The waveguide-penetration method is a method to measure the electrical properties of materials. In this method, a cylindrical object pierces a rectangular waveguide through a pair of holes at the centre of its broad walls. Then, the complex permittivity and permeability of the object are estimated from measured S-parameters after TRL calibration. This paper proposes a new calibration algorithm for the waveguide-penetration method. Reference materials with known electrical properties are fabricated in cylindrical shapes to fit into the holes in the waveguide and are used as calibration standards. The algorithm is formulated using the property of equal traces in similar matrices, and we show that at least two reference materials are needed to calibrate the system. The proposed algorithm yields a simpler means of calibration compared to TRL and is verified using measurements in the S-band. Also, the error sensitivity coefficients are derived. These coefficients give valuable information for the selection of reference materials.

In this paper, we propose an error resilience scheme for wireless video coding based on adaptive flexible macroblock ordering (FMO) and intra refresh. An FMO explicit map is generated frame-by-frame by using prior information. This information involves estimated locations of guard and burst sections in the channel and estimated effect of error propagation (EEP) from the previous frame to the current frame. In addition, the role of the current frame in propagating an error to the next frame is also considered. A suitable intra refresh rate which is adaptive to the channel state is used to reduce the dependence between frames and thus can stop the EEP. The results in experiments show that the proposed method gains some improvements in terms of peak signal-to-noise rate (PSNR) as compared with some other methods that have not considered the channel condition and the error propagation in generating an FMO map.

In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

Due to the reuse factor reduction, the same frequencies are reused in adjacent neighboring cells, which causes an attendant increase in co-channel interference (CCI). CCI has already become the limiting factor in the performance of orthogonal frequency division multiplexing (OFDM) based cellular systems. Joint maximum likelihood sequence estimation (JMLSE) based interference cancellation algorithms have been under intense research. However, despite the fact that the error probability of JMLSE is critical for analyzing the performance, to the best of our knowledge, the mathematical expression has not been derived for MQAM-OFDM yet. Direct computation of the error probability involves integrating a multi-dimensional Gaussian distribution that has no closed-form solution. Therefore, an alternative way is to upper and lower bound the error probability with computable quantities. In this paper, firstly, both the upper and the conventional lower error probability bounds of JMLSE are derived for MQAM-OFDM systems based on a genie-aided receiver. Secondly, in order to reduce the gap between the conventional lower bound and the simulation results, a tighter lower bound is derived by replacing the genie with a less generous one. Thirdly, those derived error probability bounds are generalized to the receiver diversity scheme. These error probability bounds are important new analytical results that can be used to provide rapid and accurate estimation of the BER performance over any MQAM scheme and an arbitrary number of interferers and receive antennas.

In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm2 and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

This letter investigates the performance of amplify-and-forward relaying systems using maximum ratio transmission at the source. A closed-form expression for the outage probability and a closed-form lower bound for the average bit error probability of the system are derived. Also, the approximate expressions for the outage probability and average bit error probability in the high signal-to-noise ratio regime are given, based on which the optimal power allocation strategies to minimize the outage probability and average bit error probability are developed. Furthermore, numerical results illustrate that optimizing the allocation of power can improve the system performance, especially in the high signal-to-noise ratio regime.

This paper introduces the ensemble Monte Carlo (EMC) method to study the time behavior of single-electron-based logic gates. The method is then applied to a buffer-inverter gate and the results are examined. An analytical model for time behavior at the low-temperature limit is then introduced and its results are compared with those of the EMC. Finally, a compact model for the delay-error behavior of the buffer gate is introduced.

Brain-Computer Interfaces (BCIs) are systems that translate one's thoughts into commands to restore control and communication to severely paralyzed people, and they are also appealing to healthy people. One of the challenges is to improve the performance of BCIs, often measured by the accuracy and the trial duration, or the information transfer rate (ITR), i.e., the mutual information per unit time. Since BCIs are communications between a user and a system, error control schemes such as forward error correction and automatic repeat request (ARQ) can be applied to BCIs to improve the accuracy. This paper presents reliability-based ARQ (RB-ARQ), a variation of ARQ designed for BCIs, which employs the maximum posterior probability for the repeat decision. The current results show that RB-ARQ is more effective than the conventional methods, i.e., better accuracy when trial duration was the same, and shorter trial duration when the accuracy was the same. This resulted in a greater information transfer rate and a greater utility, which is a more practical performance measure in the P300 speller task. The results also show that such users who achieve a poor accuracy for some reason can benefit the most from RB-ARQ, which could make BCIs more universal.

Channel errors may exist in Radio Frequency IDentification (RFID) systems due to low power backscattering of tags. These errors prevent the rapid identification of tags, and reducing this deterioration is an important issue. This paper presents performance analysis of various tag anti-collision algorithms and shows that the performances of RFID systems can be improved by applying a proposed robust algorithm in error-prone environments.

We find necessary and sufficient conditions for the (shifted) oversampling expansions to hold in wavelet subspaces. In particular, we characterize scaling functions with the (shifted) oversampling property. We also obtain L2 and L∞ norm estimates for the truncation and aliasing errors of the oversampling expansion.

This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. Four-parallel processing is used to achieve 12-Gbps data throughput and low hardware complexity. Also, the proposed pipelined folded Degree-Computationless Modified Euclidean (fDCME) algorithm is used to implement the key equation solver (KES) block, which provides low hardware complexity for the RS decoder. The proposed four-parallel RS decoder is implemented 90-nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can be operated at a clock frequency of 400 MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity. Therefore it can be applied in the FEC devices for next-generation high-rate WPAN systems with data rate of 10-Gbps and beyond.

In this letter, a multiuser cooperative network with multiple relays is introduced, and two decode-and-forward (DF) cooperation schemes are proposed aiming at outage-optimal and fair user scheduling, respectively. The outage probability and asymptotic expressions of symbol error probability (SEP) are derived to evaluate these two schemes. Analysis and simulations show that both schemes can achieve full diversity order, which is the combination of cooperative diversity and multiuser diversity.

In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.