In this paper, we study the performance of convolutional coding using an error-and-erasure correction Viterbi decoder for π/4-shift QDPSK mobile radio transmission. The receiver uses received signal envelope as channel state information to erase unreliable symbols instead of making explicit decision before decoding. The performance study is carried out over frequency-selective fading channel with additive white Gaussian noise, co-channel interference and propagation delay spread. The results show that decoding with symbol erasure can significantly improve the system transmission performance compared to decoding without symbol erasure.

A model for time spread-pulse position modulation (TS-PPM)/code division multiple access (CDMA) systems is presented. A TS signal is produced by a TS-filter, whose characteristic is a pseudonoise sequence in frequency domain. The error probability performance is analyzed and compared with those of on-off keying (OOK) and binary phase shift keying (BPSK). It is shown that at the same transmission speed TS-PPM is superior to TS-OOK and TS-BPSK due to the dramatic decrease of multiple access interference. The throughput of the network is analyzed, and its relation to the length of pseudonoise sequence and the packet length is also discussed.

Two types of multicast error control protocols based on a product code structure with or without interleaving are considered. The performances of these protocols are analyzed on burst error channels modeled by Gilbert's two-state Markov chain. The numerical results reveal that the interleaving does not always succeed in improving the performance of the protocol proposed in Part .

A multicast error control protocol proposed by Metzner is generalized and the performance of the proposed protocol on random error channels (binary symmetric channels) is analyzed. The proposed protocol adopts an encoding procedure based on a product code structure, whith enables each destined user terminal to decode the received frames with the Reddy-Robinson algorithm. As a result, the performance degradation due to the re-broadcasting of the replicas of the previously transmitted frames can be circumvented. The numerical results for the analysis and the simulation indicate that the proposed protocol yields higher throughput and less degradation of throughput with an increase of the number of destined terminals.

This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.

Strongly Fault-Secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly Code-Disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. This paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised.

Signature analysis using a Multiple-Input LFSR as the output response compaction circuit is widely adopted in actual BIST schemes. While aliasing probabilities for random errors are usually very small, MI-LFSRs are tend to fail detecting diagonal errors. A spot error, which include the diagonal error as a particular case, is defined as multiple bit crrors adjacent in space and in time domain. Then, shuffling of interconnection between CUT output and MI-LFSR input is studied as a scheme to prevent aliasing for such errors. The condition for preventing aliasing due to a predetermined size of single spot error is shown. Block based shuffling and the shortened one are proposed to realize required distance properties. Effect of shuffling for multiple spot errors is examined by simulation showing that shuffling is effective also for a certain extend of multiple spot errors.

The paper considers the design of two families of binary block codes developed for controlling large numbers of errors which may occur in LSI, optical disks and other devices. The semidistance codes are capable of assuring a required signal-to-noise ratio in information retrieval; the t-symmetric error correcting/all unidirectional error detecting" (t-SyEC/AUED) codes are capable of correcting t or fewer symmetric errors and also detecting any number of unidirectional errors caused by the asymmetric nature of transmission or storage madia. The paper establishes an equivalence between these families of codes, and proposes improved methods for constructing, for any values of t, a class of nonsystematic constant weight codes as well as a class of systematic codes. The constructed codes of both classes are shown to be optimal when t is O, and of asymptotically optimal order" in general cases. The number of redundant bits of the obtained nonsystematic code is of the order of (t+1/2)log2 K bits, where K is the amount of information encoded. The obtained systematic codes have redundancy of the order of (t+1)log2 K bits.

This paper presents the EXM-algorithm, which locates multiple logic design errors in a combinational circuit with multiple output. The error possibility index and the six-valued simulation method have been enhanced to be applied to multiple output circuit. The algorithm locates multiple errors even if they belong to different cone circuits, and processes faster than the conventional EX-algorithm for circuits with the similar gate sizes. Experimental results have shown that the algorithm locates all errors at high hit ratio for ISCAS benchmark circuits and some other circuits.

Runlength-limited block codes are investigated. These codes are useful for storing data in storage devices. Since most devices are not noiselss, the codes are often required to have some error-control capability. We consider runlength-limited codes that can correct or detect unidirectional byte errors. Some constructions of such codes are presented.

The purpose of our research is to get further improvement in the performance of order statistic filters. The basic idea found in our research is the use of a robust median estimator to obtain median differential order information which the classes of order statistic filter required in order to sort the input signal in the filter window. In order to give the motivation for using a median estimator in the classes of order statistic filters, we derive theorems characterizing the median filters and prove them theoretically using the characteristic that the order statistic filter has the performance for a monotonic signal equivalent with the FIR linear filter. As an application of median operation, we propose and investigate the Median Differential Order Statistic Filter to reduce impulsive noise as well as Gaussian noise and regard it as a subclass of the Order Statistic Filter. Moreover, we introduce the piecewise linear function in the Median Differential Order Statistic Filter to improve performance in terms of edge preservation. We call it the Piecewise Linear Median Differential Order Statistic Filter. The effectiveness of proposed filters is verified theoretically by computing the output Mean Square Error of the filters in parts of edge signals, impulsive noise, small amplitude noise and their combination. Computer simulations also show that the proposed filter can improve the performance in both noise (small-amplitude Gaussian noise and impulsive noise) reduction and edge preservation for one-dimensional signals.

In this paper, a type hybrid ARQ scheme with Adaptive Forward Error Correction (ARQ/AFEC) using BCH codes is proposed and analyzed. The basic idea in the proposed type hybrid ARQ/AFEC scheme is to increase the error-correcting capability of BCH code according to channel state using incremental redundancy. The incremental redundancy is the remainder ai(x) of an information frame f(x) of length n divided by a minimum polynomial mi(x) of α2i-1, where α is a primitive element of finite field GF(2l). Let gi(x) be the product of mj(x) (j=1, 2, , i) and let ci(x) be the remainder of f(x) divided by gi(x). The polynomial ci(x) is obtained from the remainders ai(x) and ci-1(x) since mi(x)and gi-1 (x) are relatively prime. Since f(x) + ci(x) is divided by gi(x), f(x) + ci(x) is the codeword of an i-error-correcting BCH code when n2l-1. So, the errors less than or equal to i bits in f(x) can be corrected if ci(x) has no error.

This letter considers a subclass of t-symmetric error correcting/all unidirectional error detecting (t-SyEC/AUED) codes in which the information is represented in an m-out-of-k coded form, which thus can be regarded as virtually systematic for practical purposes. For t3, previous researchers proposed methods for constructing codes of this subclass which are either optimal or of asymptotically optimal order. This letter proposes a new method for constructing, for any values of t, m and k, codes that are either optimal or of asymptotically optimal order. The redundancy of the obtained code is of the order tlog2k bits when mt.

Although individual segments of a natural language such as words have different importance on human interpretation of the meaning, every segment has been uniformly protected by an error-correcting code. If the importance of individual segments is defined by considering their meaning in the sentence, we can adaptively control the level of error-protection for each segment according to its importance in order to reduce errors on human interpretation of the meaning. In this paper, we propose an error-control scheme based on the varying importance of each word. We first introduce a method which determines the importance of each word and then propose an error-control scheme in which several error-correcting codes are alternately used to protect each word according to its importance. Probablity of semantic errors, that is, errors on human interpretation of the meaning, is defined and used as a criterion in mapping error-correcting codes to words possessing different importance. We theoretically formalize the problem of obtaining an optimum mapping which minimizes the probability of semantic errors under some constraint. Given a certain probability distribution of the importance of words and set of error-correcting codes, we can derive the optimum mapping. The proposed error-controlling scheme is theoretically evaluated by comparing its probability of semantic errors with that of a conventional scheme in which every word is uniformly protected by a single error-correcting code. Results show that the proposed scheme can considerably raduce the probability of semantic errors while retaining the same average transmission rate or redundancy.

Logarithmic number systems (LNS) provide a very fast computational method. Their exceptional speed has been demonstrated in signal processing and then in computer graphics. But the precision problem of LNS in computer graphics has not been fully examined. In this paper analysis is made for the problem of LNS in picture generation, in particular for circle drawing. Theoretical error analysis is made for the circle drawing. That is, some expressions are developed for the relative error variances. Then they are examined by simulation experiments. Some comparisons are also done with floating point arithmetic with equivalent word length and dynamic range. The results show that the theory and the experiments agree reasonably well and that the logarithmic arithmetic is superior to or at least comparable to the corresponding floating point arithmetic with equivalent word length and dynamic range. Those results are also verified by visual inspections of actually drawn circles. It also shows that the conversion error (from integer to LNS), which is inherent in computer graphics with LNS, does not make too much influence on the total computational error for circle drawing. But it shows that the square-rooting makes the larger influence.

In this letter, we consider a magnetic or optical recording system employing a concatenated code that consists of a runlength-limited (d, k) block code as an inner code and a byte-error-correcting code as an outer code. (d, k) means that any two consecutive ones in the code bit stream are separated by at least d zeros and by at most k zeros. The minimum separation d and the maximum separation k are imposed in order to reduce intersymbol interference and extract clock control from the received bit stream, respectively. This letter recommends to use as the outer code a unidirectional-byte-error-correcting code instead of an ordinary byte-error-correcting code. If we devise the mapping of the code symbols of the outer code onto the codewords of the inner code, we may improve the error performance. Examples of the mappings are described.

An extremely accurate and very wide-band quadrature modulator IC fabricated on a single chip using bipolar technology is presented. The characteristics of this quadrature modulator IC are much superior to conventional ones (modulation phase error and deviation from quadrature is about 1/10), and this IC is applicable to high modulation schemes such as 256 QAM. In this circuit, the phase difference between local signals input to each of two balanced modulators is detected by a phase detector, and a variable phase shifter in the local port is controlled automatically by the detected signals. This, along with the use of a wide-band variable phase shifter, enables the phase difference between the local signals input to the balanced modulators to be adaptively controlled to 90 degrees in wide frequency bands. In addition, a design method for the balanced modulators to obtain small modulation phase error is described. Based on this design method, a highly accurate quadrature modulator IC was fabricated, in which two balanced modulators, the phase detector, and the variable phase shifter were integrated on a single chip. Phase deviation from quadrature in the local signals was reduced to less than 0.3 degrees in the wide frequency bands of more tham 60 MHz. The modulation phase error of the balanced modulators wes less than 0.2 degrees at 140 MHz, and less than 2.5 degrees at up to 1.3 GHz.

A new error rate formula for narrowband Differential Quaternary Phase Shift Keyed system in a Rayleigh fading channel is obtained in closed-form. The formula predicts a non-zero error probability for noiseless reception. As predicted, the computed error rates approach some constant or floor values as the signal-to-noise ratio is increased beyond a certain limit. In the presence of various Doppler frequency shifts, an IF filter bandwidth of about one times the symbol rate is found to lead to a minimum error probability prior to the appearence of the error rate floor.

Threre are two types of nonlinear associative silicon retinas. One is a sparse Hopfield type neural network which is called a H-type retina and the other is its dual network which is called a DH-type retina. The input information sequences of H-type and HD-type retinas are given by nodes and links as voltages and currents respectively. The error correcting capacity (minimum basin of attraction) of H-type and DH-type retinas is decided by the minimum numbers of links of cutset and loop respectively. The operation principle of the regeneration is based on the voltage or current distribution of the neural field. The most important nonlinear operation in the retinas is a dynamic quantization to decide the binary value of each neuron output from the neighbor value. Also, the edge is emphasized by a line-process. The rates of compression of H-type and DH-type retinas used in the simulation are 1/8 and (2/3) (1/8) respectively, where 2/3 and 1/8 mean rates of the structural and binarizational compression respectively. We could have interesting and significant simulation results enough to make a chip.

Electromagnetic interference on a bus wiring configuration of the ISDN basic interface using metallic telecommunication lines is studied. A simple circuit to simulate terminal equipment unbalance about earth is developed for measurement purposes, based on the fact that the unbalance weakens the withstanding capability against interference. The electromagnetic interferences from low-voltage supply lines, analog telephone lines and broadcasting waves are evaluated by experiments using the circuit. The interference is measured by both induced voltage on the interface line and the error rate of the transmission signal line. Consequently, it is clarified that the basic interface is disturbed by the induced voltage, because the terminal equipment in the CCITT Recommendation I.430 has too large an unbalance about earth to maintain transmission quality. Adding to this, countermeasures to reduce interference are proposed.