It is thought that we have generally succeeded in establishing learning algorithms for neural networks, such as the back-propagation algorithm. However two major issues remain to be solved. First, there are possibilities of being trapped at a local minimum in learning. Second, the convergence rate is too slow. Chang and Ghaffar proposed to add a new hidden node, whenever stopping at a local minimum, and restart to train the new net until the error converges to zero. Their method designs newly generated weights so that the new net after introducing a new hidden node has less error than that at the original local minimum. In this paper, we propose a new method that improves their convergence rate. Our proposed method is expected to give a lower system error and a larger error gradient magnitude than their method at a starting point of the new net, which leads to a faster convergence rate. Actually, it is shown through numerical examples that the proposed method gives a much better performance than the conventional Chang and Ghaffar's method.

Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operarions, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows H symbols to be processed in parallel, where H is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols H. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H, the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

In 1989, Ahlswede and Dueck introduced a new formulation of Shannon theory called identification via channels. This paper presents a simple construction of codes for identification via channels when the probability of false identification is measured by its average. The proposed code achieves the identification capacity, and its construction does not require any knowledge of coding theory.

Motivated by the design of fault-tolerant multiprocessor interconnection networks, this paper considers the following problem: Given a positive integer t and a graph H, construct a graph G from H by adding a minimum number Δ(t, H) of edges such that even after deleting any t edges from G the remaining graph contains H as a subgraph. We estimate Δ(t, H) for the hypercube and torus, which are well-known as important interconnection networks for multiprocessor systems. If we denote the hypercube and the square torus on N vertices by QN and DN respectively, we show, among others, that Δ(t, QN) = O(tN log(log N/t + log 2e)) for any t and N (t 2), and Δ(1, DN) = N/2 for N even.

Either GMW sequence or m-sequence possesses a 2-valued auto-correlation function which helps to improve the performance of a RAKE receiver. However, their cross-correlation functions are less well controlled. Before they can be applied to a CDMA system, it is necessary to construct their sub-families (taking advantage of their large family size) which offer satisfactory cross-correlation functions. This paper studies several algorithms for constructing those quasi-optimum sub-families in terms of minimized bit error rate under co-channel interference. The study shows that the performance of resultant sub-families is sensitive to sub-family sizes and algorithms. A new criterion based on combined (even and odd) maximum cross-correlation for code selection is introduced, and highest-peak-deleting and most-peak-deleting algorithms are suggested for constructing quasi-optimum sub-families of GMW and m-sequences.

A protocol completion method is proposed to transform protocols synthesized from service specifications into error-free protocols. Communication service specifications described by message sequence charts can be synthesized into protocols. The synthesized protocols may include latent exceptional behaviors that are beyond the given service specifications. Therefore, even if the service specifications themselves are verified, these exceptional behaviors may produce protocol errors such as deadlock states or unspecified reception. Error-free protocols can be obtained from error-free service specifications by synthesizing and then completing the synthesized protocols. By taking account of each service specification through protocol completion, every exceptional behavior can be detected in the protocol entities including erroneous exceptional behaviors. This function can also be applied to resolution of feature interactions. The proposed method is applied to the synthesis of the X.227 protocol from its partial service specifications.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

This paper proposes a half-chip offset QPSK (Quadrature Phase Shift Keying) modulation CDMA (Code Division Multiple Access) scheme to allow the simple differential detection while realizing a compact spectrum in nonlinear channels for wireless LAN systems. The experimental results show the proposed scheme achieves excellent Pe (probability of error) performances in ACI (adjacent channel interference) and CCI (co-channel interference) environments. Moreover, by employing time diversity and high-coding-gain FEC (Forward Error Correction), the half-chip offset QPSK-CDMA scheme realizes an improvement of 3.0 dB (in terms of Eb/No at a Pe of 105) in Rician fading environments with a Doppler frequency fD of 10 Hz and a delay spread of 40 nsec.

Most conventional methods used in character recognition extract geometrical features, such as stroke direction and connectivity, and compare them with reference patterns in a stored dictionary. Unfortunately, geometrical features are easily degraded by blurs and stains, and by the graphical designs such as used in Japanese newspaper headlines. This noise must be removed before recognition commences, but no preprocessing method is perfectly accurate. This paper proposes a method for recognizing degraded characters as well as characters printed on graphical designs. This method extracts features from binary images, and a new similarity measure, the complementary similarity measure, is used as a discriminant function; it compares the similarity and dissimilarity of binary patterns with reference dictionary patterns. Experiments are conducted using the standard character database ETL-2, which consists of machine-printed Kanji, Hiragana, Katakana, alphanumeric, and special characters. The results show that our method is much more robust against noise than the conventional geometrical-feature method. It also achieves high recognition rates of over 97% for characters with textured foregrounds, over 99% for characters with textured backgrounds, over 98% for outline fonts and over 99% for reverse contrast characters. The experiments for recognizing both the fontstyles and character category show that it also achieves high recognition rates against noise.

McEliece and Swanson offerred an upper bound on the decorder error probability of Reed-Solomon codes. In this paper, we investigate the decorder error probability of binary linear block codes and verify its properties, and apply it to binary primitive BCH codes. It is shown that the decorder error probability of an (n,k,t) binary linear block code is determined by PE uniquely if it is a constant. We derive the decorder error probability of (n,k,t) binary primitive BCH codes with n=2m-1 and +1 and show that the decorder error probabilities of those codes are close to PE if codelengh is large and coderate is high. We also compute and analyze the decorder error probabilities of some binary primitive BCH codes.

We propose a new algorithm for minimizing the number of vertices of an approximate curve by keeping the error within a given bound (min-# problem) with the parallel-strip error criterion. The best existing algorithm which solves this problem has O (n2 log n) time complexity. Our algorithm which uses the Cone Intersection Method does not have an improved time complexity, but does have a high efficiency. In particular, for practical data such as those which represent the boundaries or the skeletons of an object, the new algorithm can solve the min-# problem in nearly O(n2) time.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.

In this paper, a new encoding/decoding scheme of multiple-valued separable balanced codes is presented. These codes have 2m information digits and m (R - 2) check digits in radices R 4, 2m - 1 information digits and m + 1 check digits in R = 3, where code-length n = Rm. In actual use of code-lengths and radices, it is shown that the presented codes are relatively efficient in comparison with multiple-valued Berger codes which are known as optimal unordered codes. Meanwhile, the optimality of multiple-valued Berger codes is discussed.

The aliasing probability was analyzed for MISRs when the error probability for each input was different. A closed form expression was derived by applying the complete weight distributions of linear codes over a Galois field and its dual codes. The aliasing probability for MISRs characterized by non-primitive polynomials was also analyzed. The inner product for binary representation of symbols was used instead of multiplication over a Galois field. The results show the perfect expression for analyzing the aliasing probability of MISRs.

The performance of decision-feedback equalization combined with maximum-likelihood detection (DFE/ML) using the fixed-delay-tree-search/decision feedback (FDTS/DF) algorithm was estimated analytically in terms of the length of the feedback-filter and the depth of the ML-detector. Performance degradation due to error propagation in the feedback-loop and in the ML-detector was taken into account by using a Markov process analysis. It was quantitatively shown that signal-to-noise-ratio (SNR) performance in high-density magnetic recording channels can be improved by combining an ML-detector with a feedback-filter and that the error propagation in the DFE channel can be reduced by using an ML-detector. Finally, it was found that near-optimum performance with regard to channel SNR and error propagation can be achieved, over the channel density range from 2 to 3, by increasing the sum of the feedback-filter length and the ML-detector depth to six bits.

Tilt margins for disk and lens for a magneto-optical (MO) head were studied for designing a disk system for use with objective lenses having numerical apertures (NA) of 0.55, 0.60, and 0.65. The tilt margins were examined to determine the aberration characteristics of objective lenses and bit error rate (BER) by recording and reproducing signal. In preparing the optical head for testing disk and lens tilt margins, the aberrations were measured by image processing from the CCD area sensor for the spot image of the focused beam, and BER dependencies on the tilting of lens and disk were obtained at the velocity of the outer diameter of the MO disk at the bit rate of 80-Mbps (1, 7 code modulation) recording. According to the aberration and BER characteristics, the limitation for effective wavefront aberration would be 0.05λ rms, the tilt margins corresponded to BER limitation at the level of 3*10-5. The disk margins for NA=0.55, 0.6, and 0.65 were 0.4, 0.2, and 0.1 degrees. The lens tilt margins for NA=0.55, 0.6, and 0.65 were 0.2, 0.1, and 0.05 degrees.

The effect of an optical hard-limiter on the performance of direct-detection optical synchronous code-division multiple-access (CDMA) systems with M-ary pulse position modulation (PPM) signaling is analyzed. Moreover, the effect of the error correction coding on the performance of direct-detection optical synchronous CDMA systems with PPM signaling is analyzed: Reed-Solomon (RS) codes and convolutional codes (CC's) with soft-decision Viterbi decoding are employed. We analyze the performance under the assumption of Poisson shot noise model for the receiver photodetector and the noise due to the detector dark currents is considered. We analyze the performance under average power and bit rate constraints. Our results show that the optical hard-limiter is not effective for improving the performance of the optical CDMA systems with PPM signaling. Moreover, RS codes are shown to be more effective than CC's with soft-decision Viterbi decoding to reduce an asymptotic floor to the error probability of the system with large M, while CC's with soft-decision Viterbi decoding is more effective than RS codes for the system with small M. Furthermore, we show that as the code rate of the error correction code increases, the required average energy to achieve the bit error probability Pb105 for the RS coded PPM/CDMA system appreciably increases compared with that for the convolutional coded PPM/CDMA system when M16.

This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

This paper is concerned with the evaluation of the block error probability Pic of a block modulation code for closest coset decoding over an AWGN channel. In most cases, the conventional union bound on Pic for closest coset decoding is loose not only at low signal-to-noise ratios but at relatively high signal-to-noise ratios. In this paper, we introduce a new upper bound on the probability of union of events by using the graph theory and we derive an improved upper bound on Pic for some block modulation codes using closest coset decoding over an AWGN channel. We show that the new bound is better than the conventional union bound especially at relatively high signal-to-noise ratios.