A soft-decision decoding algorithm for binary linear block codes is proposed. This algorithm seeks to minimize the block error probability. With careful examinations of the first hard-decision decoded results, the candidate codewords are efficiently searched for. Thus, we can reduce the decoding complexity (the number of hard-decision decodings) and lower the block error probability. Computer simulation results are presented for the (23, 12) Golay code. They show that the decoding complexity is considerably reduced and the block error probability is close to that of the maximum likelihood decoder.

We studied minority carrier collection in high-density stacked-capacitor DRAM cells using a three-dimensional device simulator. We estimated the collected charge for incident angle, location, and junction size and showed that, compared to the conventional structure by a twin-well process, an n-well-guarded cell array fabricated using a triple-well process effectively reduced the charge injected into cells. The reduction was because the n-well absorbed most of the electrons. A so-called "size-effect" did exist and smaller junctions performed better. We concluded that storage capacitance in a 256 M-bit DRAM cell could be reduced, compared to that in previous devices, which would, in turn, help reduce costs in fabricating high-density DRAM.

The performance of various ARQ protocols has recently been analyzed for multidestination environments. In all previous work, the round-trip delays between the transmitter and each of the receivers are assumed (or forced) to be equal to the maximum one, to simplify the analysis and/or the operation. This assumption obviously will sacrifice the system performance. In this paper, we evaluate the throughput efficiencies of three multidestination GBN ARQ protocols under unequal round-trip delays. In the investigated protocols, multiple copies of each data block are (re)transmitted contiguously to the receivers. Tight lower bounds are obtained for the throughput efficiencies of the schemes in which each data block is transmitted with the optimum number of copies. Results show that assuming all the round-trip delays to be equal to the maximum one may sacrifice the performance significantly. We also compare the performances of the three investigated protocols. In general, the performance becomes better as the transmitter utilizes more of the outcomes of previous transmission attempts.

As RAMs become dense, their reliability reduces because of complex interactions between memory cells and soft errors due to alpha particle radiations. In order to rectify this problem, RAM manufacturers have started incorporating on-chip (built-in) ECC. In order to minimize the area overhead of on-chip ECC, the same technology is used for implementing the check bits and the information bits. Thus the check bits are exposed to the same failure modes as the information bits. Furthermore, faults in the check bits will manifest as uncorrectable multiple errors when a soft error occurs. Therefore it is important to test the check bits for all failure modes expected of other cells. In this paper, we formulate the problem of testing RAMs with on-chip ECC capability. We than derive necessary and sufficient conditions for testing the check bits for arbitrary and adjacent neighborhood pattern sensitive faults. We also provide an efficient solution to test a memory array of N bits (including check bits) for 5-cell neighborhood pattern sensitive faults in O (N) reads and writes, with the check bits also tested for the same fault classes as the information bits.

As in other fields, the automatization of railway maintenance work is a firm requirement. The authors have developed a system detecting obstacles around a railway for practical railway inspection. The system is based on an original laser-sectioning method and characterized by high accuracy with wide view and in-motion operation. It was confirmed that a static calibration was performed at an accuracy of within 5 mm. Furthermore, a theoretical estimation predicted that dynamic errors can be eliminated within a resolution of 4 mm by means of rail movement detection. In field tests on the Chuo Line, facilities were successfully inspected at speeds up to 40km/h.

We propose a decoding algorithm for the t-EC/AUED code proposed by Böinck and Tiborg. The proposed algorithm also reveals some remarkable properties of the code.

Asymptotic bounds are considered for unidirectional byte error-correcting codes. Upper bounds are developed from the concepts of the Singleton, Plotkin, and Hamming bounds. Lower bounds are also derived from a combination of the generalized concatenated code construction and the Varshamov-Gilbert bound. As the result, we find that there exist codes of low rate better than those on the basis of Hamming distance with respect to unidirectional byte error-correction.

This paper presents two new maximum likelihood decoding (MLD) algorithms for linear codes over Z-channel, which are much more efficient than conventional exhaustive algorithms for high rate codes. In the proposed algorithms, their complexities are reduced by employing the projecting set Cs of the code, which is determined by the "projecting" structure of the code. Space and computational complexities of algorithms mainly depend upon the size of Cs which is usually several times smaller than the total number of codewords. It is shown that the upper bounds on computational complexities of decoding algorithms are in proportion to the number of parity bits and the distance between an initial estimate of the codeword and the received word, respectively, while space complexities of them are equal to the size of Cs. Lastly, numerical examples clarify the average computational complexities of the proposed algorithms, and the efficiency of these algorithms for high rate codes is confirmed.

An adaptive signal processing using Acoustic Charge Transport device, which has great potential for processing very wide band signals in real time, is investigated. It shows that adaptive system for signals of bandwidth from dc up to 500 MHz can be implemented in real time.

The effectiveness of error-control coding in a frequency-hop radio system can be increased greatly by the use of side information that is developed in the radio receiver. The transmission of test symbols provides a simple method for the derivation of side information in a slow-frequency-hop receiver. Requirements on the reliability of the side information are presented, and their implications in determining the necessary number of test symbols are described. Other methods for developing side information are reviewed briefly, and applications of side information to routing protocols for frequency-hop packet radio networks are discussed.

A narrowband interference in direct sequence spread spectrum communication systems also affects the characteristics of a delay lock loop. In this paper, the delay errors of a baseband delay lock loop (DLL) in the presence of the interference which consists of a narrowband Gaussian noise and several tones are examined, and when a filter is used to reject the interference, the characteristics of the DLL are analyzed using the Fourier method. Furthermore, from the calculation results of the delay error in case where a prediction error filter with two-sided taps is used as the rejection filter, it is shown that the filter is necessary to keep the DLL in the lock-on state.

This paper investigates a multihopping scheme for MFSK (Multilevel Frequency Shift Keying) /FH-SSMA (Frequency Hopping-Spread Spectrum Multiple Access) system. Moreover, we propose and investigate a modified decoding scheme for the coded MFSK/FH-SSMA system. In this multi-hopped MFSK/FH-SSMA system, several hopping frequencies per chip are assigned and transmitted in parallel in order to improve its frequency diversity capability for a fading channel. We theoretically analyze the performance of the multihopped MFSK/FH-SSMA system in a Rayleigh fading channel. Moreover, in the coded MFSK/FH-SSMA system, we propose a modified scheme of the error and erasure decoding of an error-correcting code. The modified decoding scheme utilizes the information of rows having the largest number of entries in the decoded time-frequency matrix. Their BER (Bit Error Rate) performance is evaluated by theoretical analysis in order to show the improvement in user capacity.

This paper's main objective is to analyze several procedures which select the model g among a set G of stochastic models to minimize the value of an information criterion in the form of L(g)H[g](zn)+(k(g)/2)c(n), where zn is the n observed data emitted by an information source θ which consists of the model gθ∈G and k(gθ) mutually independent stochastic parameters in the model gθ∈G, H[g](zn) is (-1) (the maximum log likelihood value of the data zn with respect to a model g∈G), and c(n) is a predetermined function (penalty function) of n which controls the amount of penalty for increasing the model size. The result is focused on specific performances when the information criteria are applied to the framework of so-called state decomposition. Especially, upper bounds are derived of the following two performance measures for each penalty function c(n): the error probability of the model selection, and the average Kullback-Leibler information between the true information source and the estimated information source.

A novel external clocking magnetic disk recording channel is proposed and examined. Timing not only for data recovery but for recording is given by a bit clock which is synchronized with dedicated clock marks on patterned discrete track media. Jitter of the bit clock is 2.5 ns (rms), which is good enough for data rates up to about 20 Mbit/s. Using an MR/Inductive head and PRML (Partial Response Maximum Likelihood) signal processing, an error rate of 110-6 is obtained at linear density 3146 bit/mm.

Existing algorithmic debugging methods which can locate faults under the guidance of a system have a number of shortcomings. For example, some cannot be applied to imperative languages with side effects; some can locate a faulty function but cannot locate a faulty statement; and some cannot detect faults related to missing statements. This paper presents an algorithmic critical slice-based fault-locating method for imperative languages. Program faults are first classified into two categories: wrong-value faults and missing-assignment faults. The critical slice with respect to a variable-value error is a set of statements such that (1) a wrong-value fault contained in any instruction in the critical slice may have caused that variable-value error, and (2) a wrong-value fault contained in any instruction outside the critical slice could never have caused that variable-value error. The paper also classifies errors found during program testing into three categories: wrong-output errors, missing-output errors, and infinite-loop errors with no output. It finally shows that it is possible to algorithmically locate any fault, including missing statements, for each type of error.

The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

Erasure-and-error decoding is a general form of channel decoding and is a basis of important coding schemes, such as the concatenated coding scheme and coded ARQ. However, there do not exist enough discussions on the interrelationship between erasure-and-error decoding schemes. In this paper, threshold decoding schemes are discussed in a systematic manner and compared with Forney's optimal scheme. Some confusions in known results are pointed out and new results on threshold decoding are shown.

In this paper, we provide an efficient algorithm for GMD (Generalized Minimum Distance) decoding of BCH codes over q-valued logic, when q is pl (p: prime number, l: positive integer). An algebraic errors-and-erasures decoding procedure is required to execute only one time, whereas in a conventional GMD decoding at mostd/2algebraic decodings are necessary, where d is the design distance of the code. In our algorithm, Welch-Berlekamp's iterative method is efficiently employed to reduce the number of algebraic decoding procedures. We also show a method for hardware implementation of this GMD decoding based on q-valued logic.

A technique is presented for constructing (d,k) block codes capable of detecting single bit errors and single peak-shift errors in consecutive two runs. This constrains the runlengths in the code sequences to odd numbers. The capacities and the cardinalities for finite code length of these codes are described. A technique is also proposed for constructing (d,k) block codes capable of correcting single peak-shift errors.

In this paper, we study the performance of convolutional coding using an error-and-erasure correction Viterbi decoder for π/4-shift QDPSK mobile radio transmission. The receiver uses received signal envelope as channel state information to erase unreliable symbols instead of making explicit decision before decoding. The performance study is carried out over frequency-selective fading channel with additive white Gaussian noise, co-channel interference and propagation delay spread. The results show that decoding with symbol erasure can significantly improve the system transmission performance compared to decoding without symbol erasure.