This paper analyzes performance differences between interrupt-based and polling-based asynchronous I/O interfaces in high CPU contention scenarios. It examines how the choice of I/O Interface can differ depending on the performance of NVMe SSDs, particularly when using PCIe 3.0 and PCIe 4.0-based SSDs.

In order not to disrupt a team member concentrating on his/her own task, the interrupter needs to wait for a proper time. In this research, we examined the feasibility of predicting prospective interruptible times of office workers who use PCs. An analysis of actual working data collected from 13 participants revealed the relationship between uninterruptible durations and four features, i.e. type of application software, rate of PC operation activity, activity ratio between keystrokes and mouse clicks, and switching frequency of application software. On the basis of these results, we developed a probabilistic work continuance model whose probability changes according to the four features. The leave-one-out cross-validation indicated positive correlations between the actual and the predicted durations. The medians of the actual and the predicted durations were 539 s and 519 s. The main contribution of this study is the demonstration of the feasibility to predict uninterruptible durations in an actual working scenario.

Various systems that share remote co-worker's awareness information have been proposed for realizing efficient collaborative work among distributed offices. In this study, we implemented an interruptibility sharing system in a university laboratory and assessed the observation behavior for the displayed information. Observation behavior for each target member was detected using an eye tracker to discuss the usage and effect of the system in a quantitative manner, along with the considerations of workers' job positions and relationships. The results suggested that participants observed interruptibility information approximately once an hour while at their desks. Observations were frequent during break-times rather than when the participants wanted to communicate with others. The most frequently observed targets were the participants themselves. The participants gazed the laboratory members not only in a close work relationship but also in a weak relationship. Results suggested that sharing of interruptibility information assists worker's self-reflection and contributes to the establishment of horizontal connection in an organization including members in weak work relationship.

Various DC power supply systems such as photovoltaic power generation, fuel cell and others have been gradually spreading, so that DC power distribution systems are expected as one of energy-saving technologies at houses and business-related buildings as well as data centers and factories. Under such circumstances switches for electric appliances are requested to interrupt DC current safely in DC power systems (DC 300-400V). It is well-known that DC current is much more difficult to be interrupted than AC current with current-zero. In this paper a model switch is developed and fundamental characteristics of DC current interruption in a resistive circuit is experimentally and theoretically examined. Consequently arc duration is found to be approximately a function of interrupted power rather than source voltage and circuit current. In addition arc length at its extinction is obtained by the observation of a high-speed camera. Then the arc length is found to be decided only by interrupted power like the gap length, independent of separation velocity. From these results it can be made clear that the arc form becomes arc-shaped at its extinction when the interrupted power is larger than about 500W. In addition the effect of magnetic blow-out on arc extinction is examined.

Frequently interrupting someone who is busy will decrease his or her productivity. To minimize this risk, a number of interruptibility estimation methods based on PC activity such as typing or mouse clicks have been developed. However, these estimation methods do not take account of the effect of conversations in relation to the interruptibility of office workers engaged in intellectual activities such as scientific research. This study proposes an interruptibility estimation method that takes account of the conversation status. Two conversation indices, “In conversation” and “End of conversation” were used in a method that we developed based on our analysis of 50 hours worth of recorded activity. Experiments, using the conversation status as judged by the Wizard-of-OZ method, demonstrated that the estimation accuracy can be improved by the two indices. Furthermore, an automatic conversation status recognition system was developed to replace the Wizard-of-OZ procedure. The results of using it for interruptibility estimation suggest the effectiveness of the automatically recognized conversation status.

This paper clarifies the bifurcation structure of the chaotic attractor in an interrupted circuit with switching delay from theoretical and experimental view points. First, we introduce the circuit model and its dynamics. Next, we define the return map in order to investigate the bifurcation structure of the chaotic attractor. Finally, we discuss the dynamical effect of switching delay in the existence region of the chaotic attractor compared with that of a circuit with ideal switching.

Multi-Channel MAC protocols increase network throughput because multiple data transmissions can take place simultaneously. However, existing Multi-Channel MAC protocols do not take full advantage of the multi-channel environment, because they lack a mechanism allowing wireless stations to acquire vacant channel and time resources. In this paper, we first establish the basic model of existing Multi-Channel MAC protocols to know the capability of the most important existing protocols. Next, under the condition that each station can use only two transceivers, we propose Multi-Channel MAC protocols that effectively utilize idle channels and potentially available time resources of stations by employing bursts and interrupted frame transfers. We assume a transceiver can behave as either a transmitter or a receiver but not both at the same time. Moreover, we show the effectiveness of our proposal by computer simulation. Furthermore, through the evaluation in the case that each station can use more than two transceivers, we confirm two transceivers' case is best solution in terms of both attained throughput and hardware complexity.

The paper is devoted to the experimental study of the arc plasma characteristics in SF6, N2 and CO2. To one flexible model of gas circuit breaker, short circuit experiments have been carried out considering the influence of contact gap (4–12 mm), gas pressure (1–5 atm), short circuit current (1–5 kA effective value) as well as gas species particularly. During the experiments, the arc image, arc current and arc voltage are recorded by the high speed camera, shunt and voltage transducer, respectively. It demonstrates that to the above mentioned three kinds of gases, the arc radius and arc voltage increase with the short circuit current and gas pressure normally; however, under the same experimental conditions, N2 arc holds the minimum arc radius and the maximum arc voltage, and the arc voltage of SF6 arc is the lowest.

Interrupt service routines are a key technology for embedded systems. In this paper, we introduce the standard approach for using Generalized Stochastic Petri Nets (GSPNs) as a high-level model for generating CTMC Continuous-Time Markov Chains (CTMCs) and then use Markov Reward Models (MRMs) to compute the performance for embedded systems. This framework is employed to analyze two embedded controllers with low cost and high performance, ARM7 and Cortex-M3. Cortex-M3 is designed with a tail-chaining mechanism to improve the performance of ARM7 when a nested interrupt occurs on an embedded controller. The Platform Independent Petri net Editor 2 (PIPE2) tool is used to model and evaluate the controllers in terms of power consumption and interrupt overhead performance. Using numerical results, in spite of the power consumption or interrupt overhead, Cortex-M3 performs better than ARM7.

To one double-breaker model, experimental investigation on blow open force was carried out. It demonstrates that the ratio between the emerging blow open force and arc power FB/ui decreases with the arcing time, the contact gap has less effect on FB/ui, and the characteristics of the blow open force are similar when the peak value of the short circuit current is beyond 4 kA. Then, according to the experimental data and conclusions, considering the influence of blow open force, the interruption process of molded case circuit breakers (MCCBs) was investigated. It demonstrates the blow open force has significant influence on interruption process and the proposed method is effective to evaluate new design of MCCBs.

Among the broadband wireless communication standards utilized to satisfy the demand for multimedia services, time division duplexing (TDD) is satisfactory for the asymmetric data transmission emphasized in Internet services. In this system, the transition between receiving a frame and transmitting a response must be bounded for an effective use of radio resources. However, the minimized inter-frame space-time requires high processing power. The aim of the present paper is to gain insight into the time latency at the turn-around time of a TDD operation. We also propose a simplified new processor, which is a terminal device-friendly architecture that includes prediction and preparation to support processing of burst-type traffic.

A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360 MIPS/400MFLOPS/200 MHz core--based on the Harvard bus architecture--uses 0.13/0.15-µm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.

To overcome the mobility impact on RSVP, many schemes have been proposed based on Mobile IP regional registration and passive reservation in advance. Although the regional registration and in advance reservation reduce the QoS interruption time, the latter may demand intolerable bandwidth. This letter introduces a novel approach to reduce the QoS interruption time by maximizing the localization of QoS re-establishment in the regional registration environment. The proposed scheme identifies the exact path segment affected by mobility. The QoS interruption time of the proposed scheme is comparable to its low bound without in advance reservation.

This paper proposes an independent control for parallel-connected multiple uninterruptible power supply (UPS) systems based upon a very simple control scheme. Here, the amplitude and phase angle of the output voltage are the controllable variables. With the only measurement of the output current, the active and reactive components are calculated to define the control variables. The entire system including the equations for the circuit, control and voltage limiters is well represented by a small-signal model, in which the computation of its eigenvalues constitutes the stability proof of the system. The root locus diagram gives an overall panorama of the system performance as a function of a certain gain and it aims to aid the further understanding and the design of the control. The experimental verification is carried out using a mere proportional-integral control scheme, which is a special case of the general control equation used in the theoretical analysis. For some situations, experiments show a flow of lateral current between UPS's, which causes an unbalanced current distribution. By increasing the proportional gain of the control equation for the output voltage amplitude, the lateral current can be substantially suppressed with a consequent improvement of the load sharing. Experimental results under various conditions show excellent results in terms of synchronization, load sharing and stability for three distinct output rating UPS's connected in parallel.

In order to get the knowledge of gas dynamics in interruption process of molded case circuit breakers, a quenching chamber model with gas-driven arc is proposed. The two-dimensional optical fiber digital testing system has been used to measure the arc current, arc voltage, pressure in the quenching chamber, and the movement of the arc when interrupting the 10 kA prospective current in different conditions. The influence of venting conditions, the configuration of splitter plates and gassing material characteristics on the performance of gas-driven arc has investigated. It demonstrates that the performance can be improved effectively by the ways of closing the bottom venting, adopting shorter splitter plate configuration, and POM and Nylon gassing materials.

Superscalar processors can achieve increased performance by issuing instructions Out-of-Order (OoO) from the original instruction stream. Implementing an OoO instruction scheme requires a hardware mechanism to prevent incorrectly executed instructions from updating registers values. In addition, performance decreases if data dependencies, a branch or a trap among instructions appears. To this end we propose a new mechanism named Dynamic Fast Issue (DFI) mechanism to issue instructions in an OoO fashion to multiple parallel functional units without considerable hardware complexity. The above system, which will be implemented in our Superscalar Functional Assignments Register Microprocessor(FARM), solves data dependencies, supports precise interrupt and branch prediction, which are the main problems associated with the dynamic scheduling of instructions in superscalar machines. Results are written only once,Write-once, directly into the register file (RF). To ensure that results are written in order in their appropriate output registers, a record of instruction order and state is maintained by a status buffer (STB). A 64 entries integrated register file is implemented to hold both renamed and logical registers. To recover the processor state from an interrupt or a branch miss-prediction, a status buffer (STB) and a recovery list table (RLT) are implemented. Novel aspects of the above system architecture as well as the principle underlying this process and the constraints that must be met is presented. Performance evaluation results are performed through full-pipelined-level architectural simulator and SPECint95 benchmark programs.

The complexity of designing communication protocols has lead researchers to develop various techniques for designing and verifying protocols. One of the most important techniques is a compositional technique. Using a compositional technique, a large and complex protocol is designed and verified by composing small and simple protocols which are easy to handle, design and verify. Unlike the other compositional approaches, we propose compositional techniques for simultaneously composing service specifications and protocol specifications based on Formal Description Techniques (FDTs) called LOTOS. The proposed techniques consider alternative, sequential, interrupt and parallel composition of service specifications and protocol specifications. The composite service specification and the composite protocol specification preserve the original behaviour and the correctness properties of individual service specifications and protocol specifications. We use the weak bisimulation equivalence (), to represent the correctness properties between the service specification and the protocol specification. When a protocol specification is weak bisimulation equivalent to a service specification, the protocol satisfies all the logical properties of a communication protocol as well as provides the services that are specified in the service specification.

This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.

Multimedia communications often require intramedia synchronization for video data to prevent potential playout discontinuity while still retaining satisfactory playout throughput. In this paper, we propose a novel intra-video synchronization mechanism, called the Video Smoother, particularly suitable for low-end multimedia applications, such as video conferencing. Generally, the Video Smoother dynamically adopts various playout rates according to the number of frames in the playout buffer in an attempt to compensate for the delay jitter introduced from networks. In essence, if the number of frames in the buffer exceeds a given threshold (TH), the Smoother employs a maximum playout rate. Otherwise, the Smoother employs linearly or exponentially reduced rates to eliminate playout pauses resulting from the emptiness of the playout buffer. To determine optimal THs achieving a minimum of playout discontinuity and a maximum of playout throughput under various bursty traffic, we propose an analytic model assuming incoming traffic following an Interrupted Bernoulli arrival Process (IBP). As a result, optimal THs can be analytically determined resulting in superior playout quality under various arrivals and loads of networks. Finally, we display simulation results which demonstrate that, compared to the playout without intra-video synchronization (instant playout), the Video Smoother achieves superior smooth playout and compatible throughput.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.