This paper shows that sum-of-product expression (SOP) minimization produces the generalization ability. We show this in three steps. First, various classes of SOPs are generated. Second, minterms of SOP are randomly selected to generate partially defined functions. And, third, from the partially defined functions, original functions are reconstructed by SOP minimization. We consider Achilles heel functions, majority functions, monotone increasing cascade functions, functions generated from random SOPs, monotone increasing random SOPs, circle functions, and globe functions. As for the generalization ability, the presented method is compared with Naive Bayes, multi-level perceptron, support vector machine, JRIP, J48, and random forest. For these functions, in many cases, only 10% of the input combinations are sufficient to reconstruct more than 90% of the truth tables of the original functions.

A set consisting of K subsets of Msequences of length L is called a complementary sequence set expressed by A(L, K, M), if the sum of the out-of-phase aperiodic autocorrelation functions of the sequences within a subset and the sum of the cross-correlation functions between the corresponding sequences in any two subsets are zero at any phase shift. Suehiro et al. first proposed complementary set A(Nn, N, N) where N and n are positive integers greater than or equal to 2. Recently, several complementary sets related to Suehiro's construction, such as N being a power of a prime number, have been proposed. However, there is no discussion about their inclusion relation and properties of sequences. This paper rigorously formulates and investigates the (generalized) logic functions of the complementary sets by Suehiro et al. in order to understand its construction method and the properties of sequences. As a result, it is shown that there exists a case where the logic function is bent when n is even. This means that each series can be guaranteed to have pseudo-random properties to some extent. In other words, it means that the complementary set can be successfully applied to communication on fluctuating channels. The logic functions also allow simplification of sequence generators and their matched filters.

A polyphase sequence set with orthogonality consisting complex elements with unit magnitude, can be expressed by a unitary matrix corresponding to the complex Hadamard matrix or the discrete Fourier transform (DFT) matrix, whose rows are orthogonal to each other. Its matched filter bank (MFB), which can simultaneously output the correlation between a received symbol and any sequence in the set, is effective for constructing communication systems flexibly. This paper discusses the compact design of the MFB of a polyphase sequence set, which can be applied to any sequence set generated by the given logic function. It is primarily focused on a ZCZ code with q-phase or more elements expressed as A(N=qn+s, M=qn-1, Zcz=qs(q-1)), where q, N, M and Zcz respectively denote, a positive integer, sequence period, family size, and a zero correlation zone, since the compact design of the MFB becomes difficult when Zcz is large. It is shown that the given logic function on the ring of integers modulo q generating the ZCZ code gives the matrix representation of the MFB that M-dimensional output vector can be represented by the product of the unitary matrix of order M and an M-dimensional input vector whose elements are written as the sum of elements of an N-dimensional input vector. Since the unitary matrix (complex Hadamard matrix) can be factorized into n-1 unitary matrices of order M with qM nonzero elements corresponding to fast unitary transform, a compact MFB with a minimum number of circuit elements can be designed. Its hardware complexity is reduced from O(MN) to O(qM log q M+N).

In order to implement complementary logic function with L-shaped tunneling field-effect transistors (TFETs), current drivability and subthreshold swing (SS) need to be improved more. For this purpose, high-k material such as hafnium dioxide (HfO2) has been used as gate dielectric rather than silicon dioxide (SiO2). The effects of device parameters on performance have been investigated and the design of L-shaped TFETs has been optimized. Finally, the performance of L-shaped TFET inverters have been compared with that of conventional TFET ones.

A tunneling magnetoresistive(TMR)-based logic-in- memory circuit, where storage functions are distributed over a logic-circuit plane, is proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability, any logic functions with external inputs and stored inputs can be performed by using the TMR-based resistor/transistor network. The combination of dynamic current-mode circuitry and a TMR-based logic network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of an SAD unit for MPEG encoding is discussed, and its advantages are demonstrated.

This paper considers Quasi-Reduced ordered Multi-valued Decision Diagrams with k bits (QRMDD(k)s) to represent binary logic functions. Experimental results show relations between the values of k and the numbers of nodes, the memory sizes, the numbers of memory accesses, and area-time complexity for QRMDD(k). For many benchmark functions, the numbers of nodes and memory accesses for QRMDD(k)s are nearly equal to of the corresponding Quasi-Reduced ordered Binary Decision Diagrams (QRBDDs), and the memory sizes and the area-time complexities for QRMDD(k)s are minimum when k = 2 and k = 3-6, respectively.

Binary Decision Diagrams (BDDs) are graph representation of Boolean functions. In particular, Ordered BDDs (OBDDs) are useful in many situations, because they provide canonical representation and they are manipulated efficiently. BDD packages which automatically generate OBDDs have been developed, and they are now widely used in logic design area, including formal verification and logic synthesis. Synthesis of pass-transistor circuits is one of successful applications of such BDD packages. Pass-transistor circuits are generated from BDDs by mapping each node to a selector which consists of two or four pass transistors. If circuits are generated from smaller BDDs, generated circuits have smaller number of transistors and hence save chip area and power consumption. In this paper, more generic BDDs which have no restrictions in variable ordering and variable appearance count on its paths are called Generic BDDs (GBDDs), and an algorithm for generating GBDDs is proposed for the purpose of synthesis of pass-transistor circuits. The proposed algorithm consists of two steps. At the first step, parse trees (PTs) for given Boolean formulas are generated, where a PT is a directed tree representation of Boolean formula(s) and it consists of literal nodes and operation nodes. In this step, our algorithm attempts to reduce the number of literal nodes of PTs. At the second step, a GBDD is generated for the PTs using Concatenation Method, where Concatenation Method generates a GBDD by connecting GBDDs vertically. In this step, our algorithm attempts to share isomorphic subgraphs. In experiments on ISCAS'89 and MCNC benchmark circuits, our program successfully generated 32 GBDDs out of 680 single-output functions and 4 GBDDs out of 49 multi-output functions whose sizes are smaller than OBDDs. GBDD size is reduced by 23.1% in the best case compared with OBDD.

Regular ternary logic functions are one of the most useful special classes of Kleenean functions, and a lot of research has been done on them. However, there has been little work done on incompletely specified regular ternary logic functions. This paper describes the following points: (1) Minimization of incompletely specified regular ternary logic functions. (2) A new definition of incompletely specified fuzzy switching functions and their minimization. (Concretely speaking, minimal disjunctive forms of incompletely specified fuzzy switching functions are represented in formulas of regular ternary logic functions. ) (3) Their application to fuzzy logic circuits such as fuzzy PLAs of AND-OR type.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

Signal Transition Graphs (STG'S) [1] are Petrinets [2], which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfollding, has been proposed [3], [4]. OCN's can represent both causality and concurrency between two nodes by net stryctyre. In this paper, we propose an efficient algorithm to derive a logic function by generating sub-state space of a given STG using the structural properties of OCN. The proposed algorithm can be seem as a parallel algorithm for deriving a logic function.

This paper presents Ternary Decision Diagrams which represent sets of products. This paper also presents manipulating methods for sum-of-products forms and ringsum-of-products forms using Ternary Decision Diagrams, and gives comparison results between Ternary Decision Diagrams and Binary Decision Diagrams.

In this paper, an approach to derive a logic function of asynchronous circuits from a graph-based model called Signal Transition Graphs (STG) is discussed. STG's are Petri nets, whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STG's can represent a behavior of circuit, to derive logic functions, however, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.

Truncated sum (TSUM for short) is useful for MV-PLA's realization. This paper introduces a new class of multiple-valued logic functions that are expressed by truncated sum, differential product (DPRODUCT for short), NOT and variables, where TSUM (x, y)min (xy, p1) and DPRODUCT (x, y)max (xy(p1), 0) is newly defined as the product that is derived by applying De Morgan's laws to TSUM. We call the functions T-functios. First, this paper clarifies that a set of T-functions is not a lattice. It clarifies that Lukasiewicz implication can be expressed by TSUM and NOT. It guarantees that a set of p-valued T-functios is not complete but complete with constants. Next, the speculations of the number of T-functions for less than ten radixes are derived. For eleven or more radix p, a speculation of the number of p-valued T-functions is shown. Moreover, it compares the T-functions with B-functions. The B-functions have been defined as the functions expressed by MAX, MIN, NOT and variables. As a result, it shows that a set of T-functions includes a set of B-functions. Finally, an inclusion relation among these functional sets and normality condition is shown.

The paper considers multiple-valued logic systems having the property that the ambiguity of the system increases as the ambiguity of each component increases. The partial-ordering relation with respect to ambiguity with the greatest element 1/2 and minimal elements 0, 1 or simply the ambiguity relation is introduced in the set of truth values V {0, 1/ (p1), , 1/2, , (p2) / (p1), 1}. A-monotonic p-valued logic functions are defined as p-valued logic functions monotonic with respect to the ambiguity relation. A necessary and sufficient condition for A-monotonic p-valued logic functions is presented along with the proofs, and their logic formulae using unary operators defined in the ambiguity relation are given. Some discussions on the extension of theories to other partial-ordering relations are also given.

Kleene-Stone algebra is both Kleene algebra and Stone algebra. The set of Kleene-Stone logic functions discussed in this paper is one of the models of Kleene-Stone algebra, and they can easily represent the concepts of necessity and possibility which are important concepts for many-valued logic systems. Main results of this paper are that the followings are clarified: a necessary and sufficient condition for a function to be a Kleene-Stone logic function and a formula representing the number of n-variable Kleene-Stone logic functions.