We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, dispite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 µm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 µm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.

Self-aligned InP/InGaAs heterojunction bipolar transistors (HBTs) were fabricated with emitter electrodes of 12, 22, 25, and 220 µm2 on the same wafer to investigate the influence of lateral scaling on device performance. DC characterization of these devices showed that InP/InGaAs HBTs are less subject to the emitter-size effect than GaAs-based HBTs. Common-emitter current gain β of the smallest 12-µm2 transistor was approximately 60 which is high enough for practical use. High-frequency characteristics of the transistors were almost the same in spite of the large difference in device size. Unity current-gain cutoff frequency fT of the smallest 12-µm2 transistor was as high as 163 GHz at a collector current of 2.3 mA, which ranks with the fT176 GHz achieved by the largest 220-µm2 transistor at a collector current of 45 mA. The smallest device also showed an excellent high-speed performance of fT100 GHz at submilliampere collector currents of Ic0.6 mA. The results indicate that small-lateral-dimension InP/InGaAs HBTs are applicable to high-speed ICs with low power dissipation.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

A 170-mW class GaAs Power MESFET and a 10-mW class MMIC pre-amplifier operating at very low drain bias have been developed for use in personal handy phones (PHP). The MESFET provided P0(1dB)22.5 dBm, ηadd38.8% at VDS3 V with IDS0.14 A (0.4 IDSS) at 1.9 GHz, and also provided P0(1dB)22.4 dBm, ηadd32.6% at VDS2 V with IDS0.24 A (0.6 IDSS). The MMIC using the same MESFET structure had a linear power gain of 13 dB, a linear output power of more than 10 dBm, and P0(1dB)13.7 dBm, ηadd24.3% at VDD3 V with ID30 mA at 1.9 GHz. The MESFET had a buried p-layer and our improved LDD n self-aligned structure both of which were optimized so as to satisfy a high V(BR)GDO of more than 10 V, a minimized bias dependence of S-parameters and low VK of less than 0.5 V.