This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.

In this letter, two OTAs with MOSFETs operating in the weak inversion region are proposed. One of the OTAs uses the exponential-logarithm transformation algorithm. Furthermore, the other realizes the high-linearity characteristics due to a small fluctuation of the common-terminal voltage of differential pair. The performance of the proposed OTAs was confirmed by HSPICE simulation.

Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.

As technology scales down, leakage energy accounts for a greater proportion of total energy. Applying the drowsy technique to a cache, is regarded as one of the most efficient techniques for reducing leakage energy. However, it increases the Soft Error Rate (SER), thus, many researchers doubt the reliability of the drowsy technique. In this paper, we show several reasons why the instruction cache can adopt the drowsy technique without reliability problems. First, an instruction cache always stores read-only data, leading to soft error recovery by re-fetching the instructions from lower level memory. Second, the effect of the re-fetching caused by soft errors on performance is negligible. Additionally, a considerable percentage of soft errors can occur without harming the performance. Lastly, unrecoverable soft errors can be controlled by the scrubbing method. The simulation results show that the drowsy instruction cache rarely increases the rate of unrecoverable errors and negligibly degrades the performance.

Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.

This work presents an ultra-low-voltage ultra-low-power weak inversion composite MOS transistor. The steady state power consumption and the linear swing signal of the composite transistor are comparable to a single transistor, whereas presenting very high output impedance. This work also presents two interesting applications for the composite transistor; a 1:1 current mirror and an extremely low power temperature sensor, a thermistor. Both implementations are verified in a standard 0.35-µm TSMC CMOS process. The current mirror presents high output impedance, comparable to the cascode configuration, which is highly desirable to improve gain and PSRR of amplifiers circuits, and mirroring relation in current mirrors.

We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

This letter presents a low-power switched current (SI) memory cell with CMOS-type configuration. By combining nMOS and pMOS in the SI memory cell and using a polarity discrimination circuit, we design a CMOS-type SI memory cell which eliminates the quiescent current in the SI memory cell. The simulation result shows that the CMOS-type SI memory cell consumes less power than the conventional class-AB memory cell.

This paper describes a new design concept, the Body Bias Voltage Set (BBVS), and presents the effect of the BBVS on static power, operating speed, and area overhead in an FPGA with field-programmable Vth components. A Flex Power FPGA is an FPGA architecture to solve the static power problem by the fine grain field-programmable Vth control method. Since the Vth of transistors for specific circuit blocks in the Flex Power FPGA is chosen from a set of Vth values defined by a BBVS, selection of a particular BBVS is an important design decision. A particular BBVS is chosen by selecting body biases from among several supplied body bias candidates. To select the optimal BBVS, we provide 136 BBVSs and perform a thorough search. In a BBVS of less Vth steps, the deepest reverse body bias for high-Vth transistors does not necessarily result in optimal conditions. A BBVS of 0.0 V and -0.8 V, which requires 1.65 times the original area, utilizes as little as 1/30 of the static power of a conventional FPGA without performance degradation. Use of an aggressive forward body bias voltage such as +0.6 V for lowest-Vth, performance is increased by up to 10%. Another BBVS of +0.6 V, 0.0 V, and -0.8 V reduces static power to 14.06% while maintaining a 10% performance increase, but it requires 2.75-fold area.

In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 µm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 µm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/ for the -20 to +80 temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.

As semiconductor processing technology advances, complex, high density circuits can be integrated in a chip. However, increasing energy consumption is becoming one of the most important limiting factors. Power estimation at the early stage of design is essential since design changes at later stages may significantly lengthen the design period and increase the costs. For efficient power estimation, we analyze the "key" control signals of a digital circuit and develop power models for several operational modes. The trade-off between accuracy and complexity can be made by choosing the number and the complexity of the power models. When compared with those of logic simulation based estimation, experimental results show that 13 to 15 times faster power estimation with an estimation error of about 5% is possible. We have also developed new logic-level power modeling techniques in which logic gates are levelized and several levels are selected to build power model tables. This table based method shows significant improvement in estimation accuracy and a slight improvement in efficiency when compared to a well-known previous method. The average estimation error has been reduced from 13.3% to 3.8%.

A fully integrated broadband up-conversion mixer with low power consumption is demonstrated on 90 nm CMOS technology in this paper. This mixer has a single-ended input and a multi-layer stacked Marchand balun is used for converting the differential output of the single-balanced mixer topology to a single-ended output. This balun employs inductive coupling between two metal layers and includes slotted shields to reduce substrate losses. The circuit size is 650 µm570 µm. At 22.1 GHz, the integrated mixer achieves a conversion gain of 2 dB with a maximum power dissipation of only 11.1 mW from a 1.2 V dc power supply at LO power of 5 dBm. Input referred 1-dB compression point is -14.8 dBm. The LO and RF return loss are better than 10 dB for frequencies between 20-26 GHz.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

This letter presents a novel implementation for Bus-Invert Coding called No Invert-Line Bus-Invert Coding (NIL-BIC) architecture. It not only removes the invert-lines used in previous BIC implementations, but sends the coding information without additional bus-transitions. NIL-BIC can save about 50% more bus-power than the implementations using invert-line.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeley's 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6 V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeley's 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 µm CMOS technology, 0.13 µm IBM CMOS technology and Berkeley's 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ED by 45.5% over ep-SFF. The simulations were performed in a 0.1 µm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.

Bi-stable displays form the foundation of a novel and attractive LCD technology. From now on, images can be maintained on the LCD after driving voltages have been withdrawn from the electrodes. In low frame-rate applications such as e-books, e-labels, smartcards etc., this offers a major improvement in power consumption and battery life. However, bi-stable displays require high driving voltages and complex waveforms. Furthermore, the nature of some applications doesn't allow the use of relatively large passive components. This rules out more traditional approaches for high-voltage generation with external coils or capacitors. This paper describes the design of completely integrated and programmable high-voltage generators capable of generating output voltages up to 50 V out of a 3 V supply voltage. Features like 8-bit output voltage programmability and stabilisation were implemented to make this type of high-voltage generator suitable for bi-stable display drivers. Design aspects and simulation results are discussed, as well as measurements on prototype generators implemented in the 0.7 µm 100 V I2T100 technology from AMI Semiconductor.