Fully integrated CMOS power amplifiers (PAs) with a two-winding and single-winding combined transformer (TS transformer) are presented. The general analysis of the TS transformer and other power-combining transformers, i.e., the series-combining transformer and parallel-combining transformer, is presented in terms of the transformer design parameters. Compared with other power-combining transformers, the proposed power-combining TS transformer offers high-efficiency with a compact form factor. In addition, a fully integrated CMOS PA using the TS transformer with multi-gated transistors (MGTRs) and adaptive bias circuit has been proposed to improve linearity. The proposed PAs are implemented using 65-nm CMOS technology. The implemented PA with the TS transformer achieves a saturated output power of 26.7 dBm with drain efficiency (DE) of 47.7%. The PA achieves 20.13-dBm output power with 21.4% DE while satisfying the -25-dB error vector magnitude (EVM) requirement when tested with the WLAN 802.11g signal. The implemented PA using the TS transformer with MGTRs and adaptive bias circuit achieves the -30-dB EVM requirement up to an output power of 17.13 dBm with 10.43% DE when tested using the WLAN 802.11ac signal.

Multi-Gate device technology is the promising candidate for the enhancement of device characteristics of the scaled MOSFETs. Moreover, independent-double-gate devices have been proposed to achieve flexible Vth adjustment. It is revealed that the SRAM noise margins have been increased by introducing the independent-double-gate FinFET.

In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

The off-state shunt GaAs FET, which is the most important for low distortion operation of the high power RF switch IC, is a very complicated device to analyze the RF voltage. Because the conventional measurement method has an influence on the behavior of the switch, it has not provided the correct measurement value. In this paper, we have realized a measurement method without touching the surface of the switch IC using EO-probe. As a result we achieved extremely low second and third harmonics of 70.5 dBc and 75.2 dBc, respectively at the input power of 35 dBm by adoptin SPDT switch IC composed of the multi-gate FET for the thru FET and the stacked-gate FET.