Polarization-adjusted convolutional (PAC) codes have better error-correcting performance than polar codes mostly because of the improved weight distribution brought by the convolutional pre-transformation. In this paper, we propose the parity check PAC (PC-PAC) codes to further improve error-correcting performance of PAC codes. The design principle is to establish parity check functions between bits with distinct row weights, such that information bits of lower reliability are re-protected by the PC relation. Moreover, an algorithm to select which bits to be involved in parity-check functions is also proposed to make sure that the constructed codes have fewer minimum-weight codewords. Simulation results show that the proposed PC-PAC codes can achieve nearly 0.2dB gain over PAC codes at frame error rate (FER) about 10-3 codes.

Quick Response (QR) code is a two dimensional barcode widely used in many applications. A standard QR code consists of black and white square modules, and it appears randomized patterns. By modifying the modules using certain rule, it is possible to display a logo image on the QR code. Such a QR code is called an aesthetic QR code. In this paper, we change the encoding method of the Reed-Solomon (RS) code to produce an aesthetic QR code without sacrificing its error correcting capability. The proposed method randomly produces candidates of RS blocks and finds the best one during encoding. Considering an image to be displayed, we also introduce a weighting function during random selection that classifies the visually important regions in the image. We further investigate the shape of modules which represents the image and consider the trade-off between the visual quality and its readability. As a result, we can produce a beautiful aesthetic QR code, which still can be decoded by standard QR code reader.

A self-adaptive scaled min-sum algorithm for LDPC decoding based on the difference between the first two minima of the check node messages (Δmin) is proposed. Δmin is utilized for adjusting the scaling factor of the check node messages, and simulation results show that the proposed algorithm improves the error correcting performance compared to existing algorithms.

This letter proposes extended single parity check product codes and presents their empirical performances on a Gaussian channel by belief propagation (BP) decoding algorithm. The simulation results show that the codes can achieve close-to-capacity performance in high coding rate. The code of length 9603 and of rate 0.96 is only 0.77 dB away from the Shannon limit for a BER of 10-5.

Generalized quasi-cyclic (GQC) codes form a wide and useful class of linear codes that includes thoroughly quasi-cyclic codes, finite geometry (FG) low density parity check (LDPC) codes, and Hermitian codes. Although it is known that the systematic encoding of GQC codes is equivalent to the division algorithm in the theory of Grobner basis of modules, there has been no algorithm that computes Grobner basis for all types of GQC codes. In this paper, we propose two algorithms to compute Grobner basis for GQC codes from their parity check matrices; we call them echelon canonical form algorithm and transpose algorithm. Both algorithms require sufficiently small number of finite-field operations with the order of the third power of code-length. Each algorithm has its own characteristic. The first algorithm is composed of elementary methods and is appropriate for low-rate codes. The second algorithm is based on a novel formula and has smaller computational complexity than the first one for high-rate codes with the number of orbits (cyclic parts) less than half of the code length. Moreover, we show that a serial-in serial-out encoder architecture for FG LDPC codes is composed of linear feedback shift registers with the size of the linear order of code-length; to encode a binary codeword of length n, it takes less than 2n adder and 2n memory elements.

The ITU-T J.83 Annex B is a widely adopted standard in North America for digital video and audio transmission over coaxial cable. This paper proposes a new parallel processing architecture of the parity checksum generator and syndrome generator specified in the standard for packet synchronization and error detection. The proposed parallel processing architecture removes the performance bottleneck occurring in the conventional serial processing architecture, leading to significant decrease in processing time for generating a parity checksum in transmitter and a syndrome in receiver. Implementation results show that the proposed parallel processing architecture reduces the processing time by 92% for parity checksum generation and by 81% for syndrome generation over the conventional serial processing architecture.

In this paper, an efficient partial incremental redundancy (P-IR) scheme is proposed for an H-ARQ using block type low density parity check (B-LDPC) codes. The performance of the proposed P-IR scheme is evaluated in an HSDPA system using IEEE 802.16e B-LDPC codes. Simulation results show that the proposed H-ARQ using IEEE 802.16e B-LDPC codes outperforms the H-ARQ using 3GPP turbo codes.

A new block coded modulation scheme with inter-level memory is proposed. The proposed code construction is based on the use of single parity check codes to concatenate a set of coded blocks. Simulation results show that the proposed scheme can achieve considerable coding gains while the decoding complexity is not too large.

In this paper, we present a new low-cost concurrent error detection (CED) S-Box architecture for the Advanced Encryption Standard (AES). Because the complexity and the nonlinearity, it is difficult to develop error detection algorithms for the S-Box. Conventionally, a parity checked S-Box is implemented with ROM (read only memory). In some applications, for example, smart cards, both chip size and fault detection are demanded seriously. ROM-based parity checking cannot meet the demands. We propose our CED S-Box (CEDSB) architecture for two reasons. The first is to design a S-Box without ROM. The second is to obtain a compact S-Box with real time error detection. Based on the composite field, we develop the CEDSB architecture to implement the fault detection for the S-Box. The overhead of the CED for the S-Boxes in GF((24)2) and in GF(((22)2)2) are 152 and 132 NAND gates respectively. The amount of extra gates used for the CEDSB is nearly equal to that of the ROM-based CED S-Box (131 NAND gates). The chip area of the ROM-based CED S-Box, the CEDSBs in GF((24)2), and in GF(((22)2)2) are 2996, 558, and 492 NAND gates separately. The chip area of the CEDSB is more compact than a ROM-based CED S-Box.

Effective and simply realizable rate compatible low-density parity-check (LDPC) codes are proposed. A parity check matrix is constructed with the progressively increased column weights (PICW) order and adopted to achieve a punctured LDPC coding scheme for a wide range of the code rates of the rate compatible systems. Using the proposed rate compatible punctured LDPC codes, low complex adaptive communication systems, such as wireless communication systems, can be achieved with the reliable transmissions.

This paper deals with a secret key agreement problem from correlated random numbers. It is proved that there is a pair of linear matrices that yields a secret key agreement in the situation wherein a sender, a legitimate receiver, and an eavesdropper have access to correlated random numbers. A relation between the coding problem of correlated sources and a secret key agreement problem from correlated random numbers are also discussed.

Recently, various decoding algorithms with Low Density Parity Check (LDPC) codes have been proposed. Most algorithms can be divided into a hard decision algorithm and a soft decision algorithm. The Weighted Bit Flipping (WBF) algorithm that is between a hard decision and a soft decision algorithms has been proposed. The Bootstrapped WBF and Modified WBF algorithms have been proposed to improve the error rate performance and decoding complexity of the WBF algorithm. In this letter, we apply the Bootstrap step to the Modified WBF algorithm. We show that the Bootstrapped modified WBF algorithm outperforms the WBF, Bootstrapped WBF, and Modified WBF algorithms. Moreover, we show that the Bootstrapped modified WBF algorithm has the lowest decoding complexity.

Conventional video compression methods generally require a large amount of computation in the encoding process because they perform motion estimations. In order to reduce the encoding complexity for video compression, this paper proposes a new video compression method based on low-density parity check codes. The proposed method is suitable for resource-constrained devices such as mobile phones and satellite cameras.

Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2r-(2l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

A nonlinear combiner random number generator is a general keystream generator for certain stream ciphers. The generator is composed of several linear feedback shift registers and a nonlinear function; the output is used as a keystream. A fast correlation attack is a typical attack for such keystream generators. Mihaljevi, Fossorier, and Imai have proposed an improved fast correlation attack. The attack is based on error correction of information bits only in the corresponding binary linear block code; APP threshold decoding is employed for the error correction procedure. In this letter, we propose a method which improves the success rate of their attacks with similar complexity. The method adds some intentional error to original parity check equations. Those equations are then used in APP threshold decoding.

In this paper, a Turbo codec with reduced number of iterations is proposed. By inserting an even parity-check bit every six information bit, the coder can increase the minimum distance of the codewords and the number of iterations is reduced. Furthermore, this codec accommodates automatic repeat request (ARQ) scheme easily.