We have developed the world's largest 16.7-inch hybrid in-cell touch panel. To realize the large sized in-cell touch panel, we applied a vertical Vcom system and low resistance sensor, which are JDI's original technologies. For glove touch function, we applied mutual bundled driving, which increases the signal intensity higher. The panel also has a low surface reflection, curved-shaped, and non-rectangular characteristics, which are particular requirements in the automotive market. The over 15-inch hybrid in-cell touch panel adheres to automotive quality requirements. We have also developed a force touch panel, which is a new human machine interface (HMI) based on a hybrid in-cell touch panel in automotive display. This study reports on the effect of the improvements on the in-plane variation of force touch and the value change of the force signal under different environment conditions. We also a introduce force touch implemented prototype.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

We propose, for the first time, highly reliable flash-type EEPROM cell fabrication using in-situ multiple rapid thermal processing (RTP) technology. In this study, rapid thermal oxynitridation tunnel oxide (RTONO) film formations followed by in-situ arsenic (As)-doped floating-gate polysilicon growth by rapid thermal chemical vapor deposition (RTCVD) technologies are fully utilized. The results show that after 5104 program/erase (P/E) endurance cycles, the conventional cell shows 65% narrowing of the threshold voltage (Vt) window, whereas the RTONO cell indicates narrowing of less than 20%. A large number of nitrogen atoms (1020 atoms/cm3) are confirmed by secondary ion mass spectrometry (SIMS), pile up at the SiO2/Si interface and distribute into bulk SiO2. It is considered that in the RTONO film stable Si-N bonds are formed which minimize electron trap generation as well as the neutral defect density, resulting in lower Vt shifts in P/E stress. In addition, the RTONO film reduces the number of hydrogen atoms because of final N2O oxynitridation. The SIMS data shows that by the in-situ RTCVD process As atoms (91020 atoms/cm3) are incorporated uniformly into 1000--thick film. Moreover, the RTCVD polysilicon film indicates an extremely flat surface. The time-dependent dielectric breakdown (TDDB) characteristics of interpoly oxide-nitride-oxide (ONO) film exhibited no defect-related breakdown and 5 times longer breakdown time as compared to phosphorus-doped polysilicon film. Therefore, the flash-EEPROM cell fabricated has good charge storing capability.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

Phosphorus-doped amorphous or polycrystalline silicon can yield a conformal, low resistance, thermallystable plug for the high-aspect-ratio, sub-half-micron contactholes found in current development prototypes of future 64 and 256 Mega-bit DRAMs. When directly contacted to a silicide layer, however, such as WSix found in polycide gate or bit line metallization/contact structures, the outdiffusion of phosphorus from the doped-silicon layer into the silicide can occur, resulting in an increase in resistance. The characteristics of both the doped-silicon and WSix layers influence the outdiffusion. The grain size of the doped silicon appears to control diffusion at the WSix/doped-silicon interface while the transition of WSix from an as-deposited amorphous to a post-annealed polycrystalline state appears to help cause uniform phosphorus diffusion throughout the silicide film. The results of phosphorus pre-doping of the silicide to reduce the effects of outdiffusion are dependent upon the relative material volumes and interfacial areas of the layers. Due to the effectiveness of the TiN barrier layer/Ti contact layer structure used in Al-based contacts, Ti and TiN were evaluated on their ability to prevent phosphorus outdiffusion. Ti reacts easily with doped silicon and to some extent with WSix, thereby allowing phosphorus to outdiffuse through the TiSix into the overlying WSix. TiN, however, is very effective in preventing phosphorus outdiffusion and preserving polycide interface smoothness. A WSix/TiN/Ti metallization layer on an in situ-doped (ISD) silicon layer with ISD silicon-plugged contactholes yields contact resistances comparable to P+-implanted or non-implanted WSix layers on similar ISD layers/plugs for contact sizes greater than approximately 0.5 µm but for contacts of 0.4 µm or below the trend in contact resistance is lowest for the polycide with TiN barrier/Ti contact interlayers. A 20 nm-thick TiN film retains its barrier characteristics even after a 4-hour 850 anneal and is applicable to the silicide-on-doped-silicon structures of future DRAM and other ULSI devices.